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bt829b/827b videostreamii decoders advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change. bt829bC video capture processor and scaler for tv/vcr analog input BT827BC composite video and s-video decoder the bt829b and BT827B videostream? decoders are a family of single-chip, pin- and register-compatible, composite ntsc/pal/secam video and s-video decod- ers. they are also pin and register backward compatible with the bt829a/827a family of products. low operating power consumption and power-down capabil- ity make them ideal low-cost solutions for pc video capture applications on both desktop and portable system platforms with a 3.3 v digital i/o interface. they support square pixel and ccir601 resolutions for ntsc, pal, and secam video. they have a ?exible pixel port which supports a variety of system interface con?g- urations, and they are offered in a 100-pin plastic quad flat pack (pqfp). functional block diagram distinguishing features ? single-chip composite/s-video ntsc/pal/ secam to ycrcb digitizer ? on-chip ultralock ? ? square pixel and ccir601 resolution for: C ntsc (m) C ntsc (m) without 7.5ire pedestal C pal (b, d, g, h, i, m, n, n combination) C secam ? chroma comb ?lter ? arbitrary horizontal and 5-tap vertical ?ltered scaling ? hardware closed-caption decoder ? vertical blanking interval (vbi) data pass-through ? arbitrary temporal decimation for a reduced frame-rate video sequence ? programmable hue, brightness, saturation, and contrast ? user-programmable cropping of the video window ? 2x oversampling to simplify external analog ?ltering ? two-wire inter-integrated circuit (i 2 c) bus interface ? 8- or 16-bit pixel interface ? ycrcb (4:2:2) output format ? software selectable four-input analog mux ? 4 fully programmable gpio bits ? auto ntsc/pal format detect ? automatic gain control (agc) ? 3.3 v i/o ? typical power consumption 0.85 w ? ieee 1149.1 joint test action group (jtag) interface ? 100-pin pqfp related products ? bt829a, bt856/857, bt864a/865a, bt864/ 865, bt852 applications ? multimedia ? image processing ? desktop video ? video phone ? teleconferencing ? interactive video adc ultralock and clock mux0 mux1 muxout syncdet refout yref+ yin 16 decimation lpf output luma-chroma separation and chroma output video yrefC output formatting analog mux adc cref+ cin crefC agc timing control data i 2 c jtag demodulation spatial and temporal scaling video timing unit generation xt0 xt1 40 mhz 40 mhz mux2 mux3
cop yright ? 1998 rockwell semiconductor systems, inc. all rights reserv ed. print date: march 1998 rockwell semiconductor systems, inc. reserv es the right to mak e changes to its products or speci? cations to impro v e performance, reliability , or manuf acturability . information furnished is belie v ed to be accurate and reliable. ho we v er , no responsibility is assumed for its use; nor for an y infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under an y patent or intellectual property rights of rockwell semiconductor systems, inc. rockwell semiconductor systems, inc. products are not designed or intended for use in life support appliances, de vices, or systems where malfunction of a rockwell semiconductor systems, inc. product can reasonably be e xpected to result in personal injury or death. rockwell semiconductor systems, inc. customers using or selling rockwell semiconductor systems, inc. products for use in such applications do so at their o wn risk and agree to fully indemnify rockwell semiconductor systems, inc. for an y damages resulting from such improper use or sale. bt is a re gistered trademark of rockwell semiconductor systems, inc. slc ? is a re gistered trademark of a t&t t echnologies, inc. product names or services listed in this publication are for identi? cation purposes only , and may be trademarks or re gistered trademarks of their respecti v e companies. all other marks mentioned herein are the property of their respecti v e holders. speci? cations are subject to change without notice. printed in the united states of america model number package ambient temperature range bt829bkrf 100-pin plastic quad flat pack (pqfp) 0?c to +70?c BT827Bkrf 100-pin plastic quad flat pack (pqfp) 0?c to +70?c ordering information
iii d829bdsa table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of t ables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 functional over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 bt829b video capture processor for tv/vcr analog input . . . . . . . . . . . . . . . . . . . 3 1.1.2 BT827B composite/s-video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.3 bt829b ar chitecture and partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.4 ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.5 scaling and cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.6 input inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.7 output inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.8 vbi data pass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.9 closed caption decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.10 i 2 c inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 differences between bt829a/827a and bt829b/827b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.1 the challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.2 operation principles of ultralock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 composite video input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6 y/c separation and chroma demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.7 video scaling, cropping, and t emporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.7.1 horizontal and v ertical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.7.2 luminance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.7.3 peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.7.4 chrominance scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.7.5 scaling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.7.6 image cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.7.7 cropping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.8 t emporal decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
t able of contents bt829b/827b v ideostr eam ii decoders iv d829bdsa 1.8 video adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8.1 the hue adjust register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8.2 the contrast adjust register (contrast) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8.3 the saturation adjust registers (sa t_u, sa t_v) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.8.4 the brightness register (bright) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.9 bt829b vbi data output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.9.2 over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.9.4 vbi line output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.9.5 vbi frame output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.10 closed captioning and extended data ser vices decoding . . . . . . . . . . . . . . . . . . . . . . . . 41 1.10.1 automatic chrominance gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.10.2 low color detection and removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.10.3 coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.0 electrical interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.1 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.1.1 analog signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.1.2 multiplexer considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.1.3 autodetection of ntsc or p al/secam video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1.4 flash a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1.5 a/d clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1.6 power -up operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.1.7 automatic gain controls (agc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1.8 cr ystal inputs and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.1.9 2x oversampling and input filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.2 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.2.1 output inter faces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.2.2 ycrcb pixel stream format, spi mode, 8- and 16-bit formats . . . . . . . . . . . . . . . . 56 2.2.3 synchronous pixel inter face (spi mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.2.4 synchronous pixel inter face (spi mode 2, bytestream) . . . . . . . . . . . . . . . . . . . . . 58 2.2.5 ccir601 compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.1 starting and stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.2 addressing the bt829b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.3 reading and writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.4 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4 jt ag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.1 need for functional v eri? cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.2 jt ag approach to t estability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.3 optional device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.4 v eri? cation with the t ap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.5 example bsdl listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
t able of contents bt829b/827b v ideostr eam ii decoders v d829bdsa 3.0 pc board layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1 ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1.1 power planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.1.2 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.1.3 digital signal inter connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1.4 analog signal inter connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1.5 latch-up a voidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.0 control register de? nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 0x00 device status register (st a tus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x01input format register (iform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 0x02t emporal decimation register (tdec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 0x03msb cropping register (crop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 0x04v ertical delay register , lower byte (vdela y_lo) . . . . . . . . . . . . . . . . . . . . . . . . 84 0x05v ertical active register , lower byte (v active_lo) . . . . . . . . . . . . . . . . . . . . . . . 84 0x06horizontal delay register , lower byte (hdela y_lo) . . . . . . . . . . . . . . . . . . . . . 84 0x07horizontal active register , lower byte (hactive_lo) . . . . . . . . . . . . . . . . . . . . 85 0x08horizontal scaling register , upper byte (hscale_hi) . . . . . . . . . . . . . . . . . . . . . 85 0x09horizontal scaling register , lower byte (hscale_lo) . . . . . . . . . . . . . . . . . . . . 85 0x0abrightness control register (bright) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 0x0bmiscellaneous control register (control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 0x0cluma gain register , lower byte (contrast_lo) . . . . . . . . . . . . . . . . . . . . . . . 88 0x0dchroma (u) gain register , lower byte (sa t_u_lo) . . . . . . . . . . . . . . . . . . . . . . 89 0x0echroma (v) gain register , lower byte (sa t_v_lo) . . . . . . . . . . . . . . . . . . . . . . 90 0x0fhue control register (hue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 0x10 sc loop control (scloop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 0x11white crush up count register (wc_up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 0x12output format register (oform) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 0x13v ertical scaling register , upper byte (vscale_hi) . . . . . . . . . . . . . . . . . . . . . . . 95 0x14v ertical scaling register , lower byte (vscale_lo) . . . . . . . . . . . . . . . . . . . . . . 96 0x15t est control register (test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 0x16video t iming polarity register (vpole) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 0x17id code register (idcode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 0x18agc delay register (adela y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 0x19burst delay register (bdela y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 0x1aadc inter face register (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 0x1bvideo t iming control (vtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 0x1cextended data ser vice/closed caption status register (cc_st a tus) . . . . . . . . 103 0x1dextended data ser vice/closed caption data register (cc_da t a) . . . . . . . . . . . 104 0x1ewhite crush down count register (wc_dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 0x1fsoftware reset register (sreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 0x3fprogrammable i/o register (p_io) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
t able of contents bt829b/827b v ideostr eam ii decoders vi d829bdsa 5.0 parametric information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 dc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.2 ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3 package mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.4 revision histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
list of figures bt829b/827b v ideostr eam ii decoders vii d829bdsa list of figures figure 1-1. bt829b/827b detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 1-2. bt829b/827b pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 1-3. ultralock behavior for ntsc square pixel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 1-4. y/c separation and chroma demodulation for composite video . . . . . . . . . . . . . . . . . . . 18 figure 1-5. y/c separation filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 1-6. filtering and scaling operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 1-7. optional horizontal luma low-pass filter responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 1-8. combined luma notch, 2x oversampling and optional low-pass filter response (ntsc) . . . . . . . . . . . . . . . . . . 21 figure 1-9. combined luma notch, 2x oversampling and optional low-pass filter response (pal/secam) . . . . . . . . . . . . . 21 figure 1-10. frequency responses for the four optional vertical luma low-pass filters . . . . . . . . . . 22 figure 1-11. combined luma notch and 2x oversampling filter response . . . . . . . . . . . . . . . . . . . . . 22 figure 1-12. peaking filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 1-13. luma peaking filters with 2x oversampling filter and luma notch . . . . . . . . . . . . . . . . . 24 figure 1-14. effect of the cropping and active registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 1-15. regions of the video signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 1-16. regions of the video frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 1-17. bt829b ycrcb 4:2:2 data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 1-18. bt829b vbi data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 1-19. vbi line output mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 1-20. vbi sample region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 1-21. location of vbi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 1-22. vbi sample ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 1-23. cc/eds data processing path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 1-24. cc/eds incoming signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 1-25. closed captioning/extended data services fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 1-26. coring map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 2-1. bt829b typical external circuitry with third overtone crystal oscillators (5 v vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 2-2. bt829b typical external circuitry with third overtone crystal oscillators (3.3v vddo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 2-3. clock options (3.3 v vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 2-4. clock options (5 v vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 2-5. luma and chroma 2x oversampling filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 2-6. output mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
list of figures bt829b/827b v ideostr eam ii decoders viii d829bdsa figure 2-7. ycrcb 4:2:2 pixel stream format (spi mode, 8- and 16-bits) . . . . . . . . . . . . . . . . . . . . . 56 figure 2-8. bt829b/827b synchronous pixel interface, mode 1 (spi-1) . . . . . . . . . . . . . . . . . . . . . . 57 figure 2-9. basic timing relationships for spi mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 2-10. data output in spi mode 2 (bytestream) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 2-11. video timing in spi modes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 2-12. horizontal timing signals in the spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 2-13. the relationship between scl and sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 2-14. i 2 c slave address configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 2-15. i 2 c protocol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 2-16. instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-1. example of ground plane layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 3-2. optional regulator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 3-3. typical power and ground connection diagram and parts list for 5 v i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 3-4. typical power and ground connection diagram and parts list for 3.3 v i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 5-1. clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 5-2. output enable timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 5-3. jtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 5-4. 100-pin pqfp package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
list of t ables bt829b/827b v ideostr eam ii decoders ix d829bdsa list of tables t able 1-1. videostream ii features options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 t able 1-2. pin descriptions grouped by pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 t able 1-3. pin function differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 t able 1-4. 3.3 v pin output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 t able 1-5. 3.3 v pin input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 t able 1-6. video input formats supported by the bt829b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 t able 1-7. register v alues for video input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 t able 1-8. scaling ratios for popular formats using frequency v alues . . . . . . . . . . . . . . . . . . . . . . 26 t able 2-1. pixel/pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 t able 2-2. description of the control codes in the pixel stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 t able 2-3. data output ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 t able 2-4. bt829b address matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 t able 2-5. example i 2 c data t ransactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 t able 2-6. device identi? cation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 t able 4-1. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 t able 5-1. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 t able 5-2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 t able 5-3. dc characteristics (3.3 v digital i/o operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 t able 5-4. dc characteristics (5 v only operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 t able 5-5. clock t iming parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 t able 5-6. power supply current parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 t able 5-7. output enable t iming parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 t able 5-8. jt ag t iming parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 t able 5-9. decoder per formance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 t able 5-10. bt829b datasheet revision histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
list of t ables bt829b/827b v ideostr eam ii decoders x d829bdsa
1 d829bdsa 1.0 functional description 1.1 functional over view rockwell s v ideostream ii products are a f amily of single-chip, pin-and re gister - compatible solutions for processing analog ntsc/p al/secam video into digi- tal 4:2:2 ycrcb video. the y pro vide a comprehensi v e choice of capabilities to enable the feature set and cost to be tailored to dif ferent system hardw are con? gu- rations. all solutions are housed in a 100-pin pqfp package. a detailed block diagram is sho wn in figure 1-1 .
2 1.0 functional description 1.1 functional over view bt829b/827b v ideostr eam ii decoders d829bdsa figure 1-1. bt829b/827b detailed block diagram muxout mux0 mux1 xt1o xt1i xt0o xt0i clkx1 clkx2 rst sd a i2ccs scl qclk hreset vreset a ctive field cbfla g d v alid video scaling input interf ace output interf ace y/c separ ation and chroma demodulation video i 2 c interf ace oe vd[15:8] vd[7:0] syncdet a gccap refout yrefC yin yref+ crefC cin cref+ clevel cloc k interf ace jt a g interf ace and cropping adjustments c a/d y a/d ov ersampling lo w-p ass filter y/c separ ation chroma demod hue , satur ation, and br ightness adjust hor iz ontal and v er tical filter ing and scaling output f or matting video timing control i 2 c cloc king jt a g tdo tdi tms tck trst mux2 ccv alid v a ctive agc and mux3 sync detect
v ideostr eam ii decoders 3 1.0 functional description bt829b/827b d829bdsa 1.1 functional over view 1.1.1 bt829b video capture processor for tv/vcr analog input the bt829b v ideo capture processor is a fully inte grated single-chip decoding and scaling solution for analog ntsc/p al/secam input signals from tv tun- ers, vcrs, cameras, and other sources of composite or y/c video. it is the second generation front-end input solution for lo w-cost pc video/graphics systems that deli v er complete inte gration and high-performance video synchronization, y/c separation, and ? ltered scaling. the bt829b has all the mix ed signal and dsp cir - cuitry required to con v ert an analog composite w a v eform into a scaled digital video stream, supporting a v ariety of video formats, resolutions, and frame rates. 1.1.2 BT827B composite/s-video decoder the BT827B pro vides full composite and s-v ideo capability along with horizontal scaling. v ertical scaling can only be implemented by line-dropping. the synchronous pix el interf ace (spi) is common to both pin-compatible de vices, which enables implementation of a single system hardw are design. similarly , a common i 2 c re gister set allo ws a single piece of dri v er code to be written for softw are control of both options. t able 1-1 compares bt829b and BT827B features. t able 1-1. videostream ii features options feature options bt829b BT827B composite video decoding x x s-video decoding x x secam video x x hardware closed caption decode x x 3.3 v digital i/o x x filtered v ertical scaling x
4 1.0 functional description 1.1 functional over view bt829b/827b v ideostr eam ii decoders d829bdsa 1.1.3 bt829b architecture and partitioning the bt829b has been de v eloped to pro vide the most cost-ef fecti v e, high-quality video input solution. it is used for lo w-cost multimedia subsystems that inte grate both graphics display and video capabilities. the feature set of the bt829b sup- ports a video/graphics system partitioning which optimizes the total cost of a sys- tem con? gured both with and without video capture capabilities. this enables system v endors to easily of fer products with v arious le v els of video support using a single base-system design. as graphics chip v endors mo v e from graphics-only to video/graphics copro- cessors, and e v entually to single-chip video/graphics processor implementations, the ability to ef ? ciently use silicon and package pins to support both graphics acceleration, video playback acceleration, and video capture becomes critical. this problem becomes more acute as the race to w ards higher performance graph- ics requires more and more package pins to be consumed for wide 64-bit memory interf aces and glueless local b us interf aces. the bt829b minimizes the cost of video capture function inte gration in tw o w ays. first, recognizing that ycrcb to rgb color space con v ersion is a required feature of multimedia controllers for acceleration of digital video playback, the bt829b a v oids redundant functionality and allo ws the do wnstream controller to perform this task. second, the bt829b can minimize the number of interf ace pins required by a do wnstream multimedia controller in order to k eep package costs to a minimum. the bt829b can also output all timing and data signals at 3.3 v le v els. controller systems designed to tak e adv antage of these features allo w video capture capability to be added to the base system in a modular f ashion using only a single inte grated circuit (ic). the BT827B is tar geted at system con? gurations using video processors which typically inte grate the scaling function. 1.1.4 ultralock the bt829b and BT827B emplo y a proprietary technique kno wn as ultralock to lock to the incoming analog video signal. it will al w ays generate the required number of pix els per line from an analog source in which the line length can v ary by as much as a fe w microseconds. ultralock s digital locking circuitry enables the v ideostream decoders to quickly and accurately lock on to video signals, re g ardless of their source. since the technique is completely digital, ultralock can recognize unstable signals caused by vcr headswitches or an y other de via- tion and adapt the locking mechanism to accommodate the source. ultralock uses nonlinear techniques which are dif ? cult, if not impossible, to implement in genlock systems. and unlik e linear techniques, it adapts the locking mechanism automatically .
v ideostr eam ii decoders 5 1.0 functional description bt829b/827b d829bdsa 1.1 functional over view 1.1.5 scaling and cropping the bt829b can reduce the video image size in both horizontal and v ertical direc- tions independently using arbitrarily selected scaling ratios. the x and y dimen- sions can be scaled do wn to one-sixteenth of the full resolution. horizontal scaling is implemented with a 6-tap interpolation ? lter , while up to 5-tap interpo- lation is used for v ertical scaling with a line store. the BT827B supports v ertical scaling by line-dropping. the video image can be arbitrarily cropped by programming the a ctive ? ag to reduce the number of acti v e scan lines and acti v e horizontal pix els per line. the bt829b and BT827B also support a temporal decimation feature that reduces video bandwidth by allo wing frames or ? elds to be dropped from a video sequence at re gular b ut arbitrarily selected interv als. 1.1.6 input interface analog video signals are input to the bt829b/827b via a four -input multiple x er that can select between four composite source inputs or between three composite and a single s-v ideo input source. when an s-v ideo source is input to the bt829b, the luma component is fed through the input analog multiple x er , and the chroma component is fed directly into the c-input pin. an a gc circuit enables the bt829b/827b to compensate for reduced amplitude in the analog signal input. the clock signal interf ace consists of tw o pairs of pins for crystal connection and tw o clock output pins. one pair of crystal pins is for connection to a 28.64 mhz (8*ntsc fsc) crystal which is selected for ntsc operation. the other is for p al operation with a 35.47 mhz (8*p al fsc) crystal. either of the tw o crystal frequencies can be selected to generate clkx1 and clkx2 output signals. clkx2 operates at the full crystal frequenc y (8*fsc), whereas clkx1 operates at half the crystal frequenc y (4*fsc). either fundamental or third har - monic crystals may be used. alternati v ely , cmos oscillators may be used. 1.1.7 output interface the bt829b and BT827B support a synchronous pix el interf ace (spi) mode. the spi supports a ycrcb 4:2:2 data stream o v er an 8- or 16-bit-wide path. when the pix el output port is con? gured to operate 8-bits wide, 8 bits of chromi- nance data are output on the ? rst clock c ycle follo wed by 8 bits of luminance data on the ne xt clock c ycle for each pix el. t w o clocks are required to output one pix el in this mode, thus a 2x clock is used to output the data. the bt829b/827b outputs all horizontal and v ertical blanking pix els in addi- tion to the acti v e pix els synchronous with clkx1 (16-bit mode) or clkx2 (8- bit mode). it is also possible to insert control codes into the pix el stream using chrominance and luminance v alues that are outside the allo w able chroma and luma ranges. these control codes can be used to ? ag video e v ents such as a ctive, hreset , and vreset . decoding these video e v ents do wnstream enables the video controller to eliminate pins required for the corresponding video control signals. both bt829b and BT827B can output (or recei v e) all digital timing, clock, and data signals at either 5 v or 3.3 v le v els for connection to 5 v or 3.3 v graphics/video controllers.
6 1.0 functional description 1.1 functional over view bt829b/827b v ideostr eam ii decoders d829bdsa 1.1.8 vbi data pass-through the bt829b/827b pro vides vbi data passthrough capability . the vbi re gion ancillary data is captured by the video decoder and made a v ailable to the system for subsequent softw are processing. the bt829b/827b may operate in a vbi line output mode, in which the vbi data is only made a v ailable during select lines. this mode of operation is intended to enable capture of vbi lines containing ancillary data as well as processing normal ycrcb video image data. in addition, the bt829b/827b supports a vbi frame output mode, in which e v ery line in the video signal is treated as if it w as a v ertical interv al line and no image data is out- put. this mode of operation is designed for use in still-frame capture/processing applications. 1.1.9 closed caption decoding the bt829b and BT827B pro vide a closed captioning (cc) and extended data services (eds) decoder . data presented to the video decoder on the cc and eds lines is decoded and made a v ailable to the system through the cc_d a t a and ccst a tus re gisters. 1.1.10 i 2 c interface the bt829b/827b re gisters are accessed via a tw o-wire i 2 c interf ace. the bt829b/827b operates as a sla v e de vice. serial clock and data lines, scl and sd a, transfer data from the b us master at a rate of 100 kbits/s. chip select and reset signals are also a v ailable to select one of tw o possible bt829b/827b de vices in the same system and to set the re gisters to their def ault v alues.
v ideostr eam ii decoders 7 1.0 functional description bt829b/827b d829bdsa 1.2 pin descriptions 1.2 pin descriptions figure 1-2 details the bt829b and BT827B pinout. t able 1-2 pro vides pin numbers, names, input and output functions, and descriptions. figure 1-2. bt829b/827b pinout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 numxtal vreset field gnd vdd agnd clevel crefC vaa agnd n/c n/c n/c cin agnd vaa cref+ n/c yrefC agnd vaa syncdet agnd mux[1] agnd mux[0] agnd muxout yin n/c gnd clkx2 oe clkx1 vdd gnd gnd qclk pwrdn cbflag ccvalid vactive oepole dvalid active hreset gnd tdo gnd tck trst tms tdi vdd gnd vpos agccap vneg refout vaa mux[2] n/c agnd vaa yref+ mux[3] vddo vd[15] vd[14] vd[13] vd[12] vd[11] vd[10] vd[9] vd[8] vdd gnd vd[7] vd[6] vd[5] vd[4] vd[3] vd[2] vd[1] vd[0] vddo gnd xt0i xt0o rst xt1i xt1o sda scl i2ccs vddo gnd vddo gnd vdd bt829b/827b
8 1.0 functional description 1.2 pin descriptions bt829b/827b v ideostr eam ii decoders d829bdsa t able 1-2. pin descriptions grouped by pin function (1 of 4) pin # i/o pin name description input stage pins 45, 50, 55, 57 i mux[3:0] analog composite video inputs to the on-chip input multiplexer . they are used to select between four composite sour ces or three composite and one s-video sour ce. unused pins should be connected to gnd. 53 o muxout the analog video output of the 4-to-1 multiplexer . connected to the yin pin. 52 i yin the analog composite or luma input to the y -adc. 67 i cin the analog chroma input to the c-adc. 59 i syncdet the sync stripper input generates timing information for the agc cir cuit. can be optionally connected through a 0.1 m f capacitor to the same sour ce as the y -adc, to maintain compatibility with bt829 board layouts. a 1 m w bleeder resistor can be connected to ground, to maintain compatibility with bt829 board layouts. for new bt829b designs, this pin may be connected to v aa. 41 a agccap the agc time constant control capacitor node. must be connected to a 0.1 m f capac- itor to ground. 43 o refout output of the agc which drives the yref+ and cref+ pins. 49 a yref+ the top of the reference ladder of the y -adc. this should be connected to refout . 62 a yrefC the bottom of the reference ladder of the y -adc. this should be connected to analog ground (agnd). 64 a cref+ the top of the reference ladder of the c-adc. this should be connected to refout . 73 a crefC the bottom of the reference ladder of the c-adc. this should be connected to analog ground (agnd). 74 a clevel an input to provide the dc level reference for the c-adc. for compatibility with bt829 board layouts, the 30 k w divider resistors may be maintained. note: this pin should be left to ? oat for new bt829b designs. 51 a n/c no connect. 46 a n/c no connect. 63, 68 a n/c no connect. 70 a n/c no connect. 69 a n/c no connect. i 2 c interface pins 19 i scl the i 2 c serial clock line. 18 i/o sda the i 2 c serial data line. 14 i i2ccs the i 2 c chip select input (ttl compatible). this pin selects one of two bt829b devices in the same system. this pin is internally pulled to ground with an effective 18 k w resistance. 15 i rst reset control input (ttl compatible). a logical 0 for a minimum of four consecutive clock cycles resets the device to its default state. a logical 0 for less than eight xt al cycles will leave the device in an undetermined state.
v ideostr eam ii decoders 9 1.0 functional description bt829b/827b d829bdsa 1.2 pin descriptions video timing unit pins 82 o hreset horizontal reset output (ttl compatible). this signal indicates the beginning of a new line of video. this signal is 64 clkx1 clock cycles wide. the falling edge of this output indicates the beginning of a new scan line of video. this pin may be de? ned in pixels as opposed to clkx1 cycles. refer to the hsfmt bit in the vtc register . note: the polarity of this pin is programmable through the vpole register . 79 o vreset v ertical reset output (ttl compatible). this signal indicates the beginning of a new ? eld of video. this signal is output coincident with the rising edge of clkx1, and is normally 6 lines wide. the falling edge of vreset indicates the beginning of a new ? eld of video. note: the polarity of this pin is programmable through the vpole register . 83 o active active video output (ttl compatible). this pin can be programmed to output the composite active or horizontal active signal via the vtc register . it is a logical high during the active/viewable periods of the video stream. the active region of the video stream is programmable. note: the polarity of this pin is programmable through the vpole register . 94 o qclk quali? ed clock output. this pin provides a rising edge only during valid, active pixel data. this output is generated from clkx1 (or clkx2 in 8-bit mode), dv alid and, if programmed, active. the phase of qclk is inverted from the clkx1 (or clkx2) to ensure adequate setup and hold time with respect to the data outputs. qclk is not output during control codes when using spi mode 2. 98 i oe output enable control (ttl compatible). all video timing unit output pins and all clock inter face output pins contain valid data following the rising edge of clkx2, after oe has been asserted low . this function is asynchronous. the three-stated pins include: vd[15:0], hreset , vreset , active, dv alid, cbflag, field, qclk, clkx1, and clkx2. see the oes bits in the oform register to disable subgroups of output pins. 78 o field odd/even field output (ttl compatible). a high state on the field pin indicates that an odd ? eld is being digitized. note: the polarity of this pin is programmable through the vpole register . 89 o cbflag cb data identi? er (ttl compatible). a high state on this pin indicates that the current chroma byte contains cb chroma information. note: the polarity of this pin is programmable through the vpole register . 2C9 o vd[15:8] digitized video data outputs (ttl compatible). vd[0] is the least signi? cant bit of the bus in 16-bit mode. vd[8] is the least signi? cant bit of the bus in 8-bit mode. the information is output with respect to clkx1 in 16-bit mode, and clkx2 in 8-bit mode. in mode 2, this port is con? gured to output control codes as well as data. when data is output in 8-bit mode using vd[15:8], vd[7:0] can be used as general purpose i/o pins. see the p_io register . 22C29 i/o vd[7:0] 84 o dv alid data v alid output (ttl compatible). this pin indicates when a valid pixel is being output onto the data bus. the bt829b digitizes video at eight times the subcarrier rate, and outputs scaled video. therefore, there are more clocks than valid data. dv alid indicates when valid pixel data is being output. note: the polarity of this pin is programmable through the vpole register . 87 o ccv alid a logical low on this pin indicates that the cc fifo is half full (8 characters). this pin may be disabled. this open drain output requires a pullup resistor for proper opera- tion. however , if closed captioning is not implemented, this pin may be left uncon- nected. t able 1-2. pin descriptions grouped by pin function (2 of 4) pin # i/o pin name description
10 1.0 functional description 1.2 pin descriptions bt829b/827b v ideostr eam ii decoders d829bdsa 91 i pwrdn a logical high on this pin puts the device into power -down mode. this is equivalent to programming clk_sleep high in the adc register . 86 o v active v ertical blanking output (ttl compatible). the falling edge of v active indicates the beginning of the active video lines in a ? eld. this occurs vdela y/2 lines after the ris- ing edge of vreset . the rising edge of v active indicates the end of active video lines and occurs active_lines/2 lines after the falling edge of v active. v active is output following the rising edge of clkx1. note: the polarity of the pin is programmable through the vpole register . 85 i oepole a logical low on this pin allows the bt829b/827b to power up in the same manner as the bt829/827. a logical high on this pin, followed by a device reset will trist a te the video outputs, sync outputs, and clock outputs. cloc k interface pins 12 a xt0i clock zero pins. a 28.64 mhz (8*fsc) fundamental (or third harmonic) cr ystal can be tied directly to these pins, or a single-ended oscillator can be connected to xt0i. cmos level inputs must be used. this clock sour ce is selected for ntsc input sour ces. when the chip is con? gured to decode p al but not ntsc (and therefore only one clock sour ce is needed), the 35.47 mhz sour ce is connected to this port (xt0). 13 a xt0o 16 a xt1i clock one pins. a 35.47 mhz (8*fsc) fundamental (or third harmonic) cr ystal can be tied directly to these pins, or a single-ended oscillator can be connected to xt1i. cmos level inputs must be used. this clock sour ce is selected for p al input sour ces. if only ntsc or p al is being decoded, and therefore only xt0i and xt0o are con- nected to a cr ystal, xt1i should be tied either high or low , and xt1o must be left ? oating. 17 a xt1o 97 o clkx1 1x clock output (ttl compatible). the frequency of this clock is 4*fsc (14.31818 mhz for ntsc or 17.73447 mhz for p al). 99 o clkx2 2x clock output (ttl compatible). the frequency of this clock is 8*fsc (28.63636 mhz for ntsc, or 35.46895 mhz for p al). 80 i numxt al cr ystal format pin. this pin is set to indicate whether one or two cr ystals are present so that the bt829b can select xt1 or xt0 as the default in auto format mode. a logi- cal 0 on this pin indicates one cr ystal is present. a logical 1 indicates two cr ystals are present. this pin is internally pulled down to ground with an effective 18 k w resis- tance. jt a g pins 34 i tck t est clock (ttl compatible). used to synchronize all jt ag test structures. when jt ag operations are not being per formed, this pin must be driven to a logical low . 36 i tms t est mode select (ttl compatible). jt ag input pin whose transitions drive the jt ag state machine through its sequences. when jt ag operations are not being per - formed, this pin must be left ? oating or tied high. 37 i tdi t est data input (ttl compatible). jt ag pin used for loading instruction into the t ap controller or for loading test vector data for boundar y-scan operation. when jt ag operations are not being per formed, this pin must be left ? oating or tied high. 32 o tdo t est data output (ttl compatible). jt ag pin used for verifying test results of all jt ag sampling operations. this output pin is active for certain jt ag operations and will be three-stated at all other times. t able 1-2. pin descriptions grouped by pin function (3 of 4) pin # i/o pin name description
v ideostr eam ii decoders 11 1.0 functional description bt829b/827b d829bdsa 1.2 pin descriptions 35 i trst t est reset (ttl compatible). jt ag pin used to initialize the jt ag controller . this pin is tied low for normal device operation. when pulled high, the jt ag controller is ready for device testing. p o wer and gr ound pins 10, 38, 76, 88, 96 p vdd +5 v power supply for digital cir cuitr y . all vdd pins must be connected together as close to the device as possible. a 0.1 m f ceramic capacitor should be connected between each group of vdd pins and the ground plane as close to the device as possible. 1, 20, 30, 92 p vddo + 3.3 v power supply for 3.3 v digital cir cuitr y . all vddo pins must be connected together as close to the device as possible. a 0.1 m f ceramic capacitor should be connected between each group of vddo pins and the ground plane, as close to the device as possible. 40, 44, 48, 60, 65, 72 p v aa +5 v , vpos +5 v power supply for analog cir cuitr y . all v aa pins and vpos must be connected together as close to the device as possible. a 0.1 m f ceramic capacitor should be connected between each group of v aa pins and the ground plane as close to the device as possible. 11, 21, 31, 33, 39, 77, 81, 90, 93, 95, 100 g gnd ground for digital cir cuitr y . all gnd pins must be connected together as close to the device as possible. 42, 47, 54, 56, 58, 61, 66, 71, 75 g agnd, vneg ground for analog cir cuitr y . all agnd pins and vneg must be connected together as close to the device as possible. i/o column legend: i = digital input o = digital output i/o = digital bidirectional a = analog g = ground p = power t able 1-2. pin descriptions grouped by pin function (4 of 4) pin # i/o pin name description
12 1.0 functional description 1.3 differences between bt829a/827a and bt829b/827b bt829b/827b v ideostr eam ii decoders d829bdsa 1.3 differences between bt829a/827a and bt829b/827b while both bt829a/827a and bt829b/827b video decoders are pin and softw are compatible, please note the dif ferences, as described in t able 1-3 . a 3.3 v mode has been added which allo ws the bt829b to interf ace to 3.3 v graphic/video controllers without the use of 5 v to 3.3 v le v el translators. see figure 3-4 for typical po wer and ground connections when in 3.3 v i/o mode. the pins listed in t able 1-4 can output 3.3 v signal le v els when pins 1, 20, 30, and 92 (vddo) are connected to a 3.3 v po wer supply . t able 1-3. pin function differences pins bt829a/ 827a bt829b/ 827b comments 1, 20, 30, 92 vdd vddo for 3.3 v i/o, connect the pins to the 3.3 v supply . for 5 v i/o, connect these pins to the 5 v supply . t able 1-4. 3.3 v pin output pin number pin name 82 hreset 79 vreset 83 a ctive 94 qclk 78 field 89 cbfla g 2C9 vd[15:8] 22C29 vd[7:0] 84 d v alid 87 ccv alid 86 v a ctive 97 clkx1 99 clkx2 32 tdo
v ideostr eam ii decoders 13 1.0 functional description bt829b/827b d829bdsa 1.3 differences between bt829a/827a and bt829b/827b the pins sho wn in t able 1-5 can recei v e 3.3 v signal le v els when pins 1, 20, 30, and 92 (vddo) are connected to a 3.3 v po wer supply: when using the bt829b/827b in the 3.3 v i/o mode with the third o v ertone crystal oscillators, the tank circuit required is dif ferent to the tank circuit when in 5 v i/o mode. see figures 2-1 , 2-2 , 2-3 , and 2-4 . t able 1-5. 3.3 v pin input pin number pin name 19 scl 18 sd a 14 i2ccs 15 rst 98 oe 91 pwrdn 85 oepole 80 numxt al 34 tck 36 tms 37 tdi 35 trst
14 1.0 functional description 1.4 ultralock bt829b/827b v ideostr eam ii decoders d829bdsa 1.4 ultralock 1.4.1 the challenge the line length (the interv al between the midpoints of the f alling edges of suc- ceeding horizontal sync pulses) of analog video sources is not constant. f or a sta- ble source such as a studio grade video source or test signal generators, this v ariation is v ery small: 2 ns. ho we v er , for an unstable source such as a vcr, laser disk player , or tv tuner , line length v ariation is as much as a fe w microsec- onds. digital display systems require a ? x ed number of pix els per line, despite these v ariations. the bt829b emplo ys a technique kno wn as ultralock to implement locking to the horizontal sync and the subcarrier of the incoming analog video signal and generating the required number of pix els per line. 1.4.2 operation principles of ultralock ultralock is based on sampling, using a ? x ed-frequenc y stable clock. because the video line length will v ary , the number of samples generated using a ? x ed-fre- quenc y sample clock will also v ary from line-to-line. if the number of generated samples-per -line is al w ays greater than the number of samples-per -line required by the particular video format, the number of acquired samples can be reduced to ? t the required number of pix els per line. the bt829b requires an 8*fsc (28.64 mhz for ntsc and 35.47 mhz for p al) crystal or oscillator input signal source. the 8*fsc clock signal, or clkx2, is di vided do wn to clkx1 internally (14.32 mhz for ntsc and 17.73 mhz for p al). both clkx2 and clkx1 are made a v ailable to the system. ultralock operates at clkx1 although the input w a v eform is sampled at clkx2 then lo w- pass ? ltered and decimated to clkx1 sample rate. at a 4*fsc (clkx1) sample rate there are 910 pix els for ntsc and 1,135 pix- els for p al/secam within a nominal line time interv al (63.5 m s for ntsc and 64 m s for p al/secam). f or square pix el ntsc and p al/secam formats there should only be 780 and 944 pix els-per -video line, respecti v ely . this is because the square pix el clock rates are slo wer than a 4*fsc clock rate: for e xample, 12.27 mhz for ntsc and 14.75 mhz for p al. ultralock accommodates line length v ariations from nominal in the incoming video by al w ays acquiring more samples (at an ef fecti v e 4*fsc rate) than are required by the particular video format. it then outputs the correct number of pix- els per line. ultralock then interpolates the required number of pix els so that it maintains the stability of the original image, despite v ariation in the line length of the incoming analog w a v eform. figure 1-3 illustrates three successi v e lines of video being decoded for square pix el ntsc output. the ? rst line is shorter than the nominal ntsc line time interv al of 63.5 m s. on this ? rst line, a line time of 63.2 m s sampled at 4*fsc (14.32 mhz) generates only 905 pix els. the second line matches the nominal line time of 63.5 m s and pro vides the e xpected 910 pix els. finally , the third line is too long at 63.8 m s within which 913 pix els are generated. in all three cases, ultralock outputs only 780 pix els.
v ideostr eam ii decoders 15 1.0 functional description bt829b/827b d829bdsa 1.4 ultralock ultralock can be used to e xtract an y programmable number of pix els from the original video stream as long as the sum of the nominal pix el line length (910 for ntsc and 1,135 for p al/secam) and the w orst case line length v ariation from nominal in the acti v e re gion is greater than or equal to the required number of output pix els per line, for e xample: note: f or stable inputs, ultralock guarantees the time between the f alling edges of hreset only to within one pix el. ultralock does, ho we v er , guarantee the number of acti v e pix els in a line as long as the stated relationship holds. figure 1-3. ultralock behavior for ntsc square pixel output analog waveform 63.2 m s 63.5 m s 63.8 m s 905 pixels 910 pixels 913 pixels line length pixels per line 780 pixels 780 pixels 780 pixels pixels sent to the fifo by ultralock p n o m p v a r + p d e s i r e d 3 where: p nom = nominal number of pix els per line at 4*fsc sample rate (910 for ntsc, 1,135 for pal/secam) p var = variation of pixel count from nominal at 4*fsc (can be a positive or negative number) p desired = desired number of output pix els per line
16 1.0 functional description 1.5 composite video input formats bt829b/827b v ideostr eam ii decoders d829bdsa 1.5 composite video input formats the bt829b supports se v eral composite video input formats. t able 1-6 speci? es the dif ferent video formats and some of the countries in which each format is used. t able 1-6. video input formats supported by the bt829b format lines fields f sc country ntsc-m 525 60 3.58 mhz u.s., many others ntsc-japan (1) 525 60 3.58 mhz japan p al-b 625 50 4.43 mhz many p al-d 625 50 4.43 mhz china p al-g 625 50 4.43 mhz many p al-h 625 50 4.43 mhz belgium p al-i 625 50 4.43 mhz great britain, others p al-m 525 60 4.43 mhz brazil p al-n 625 50 4.43 mhz paraguay , uruguay p al-n combination 625 50 3.58 mhz argentina secam 625 50 4.406 mhz 4.250 mhz eastern europe, france, middle east notes: (1). ntsc-japan has 0 ire setup.
v ideostr eam ii decoders 17 1.0 functional description bt829b/827b d829bdsa 1.5 composite video input formats the video decoder must be programmed appropriately for each of the composite video input formats. t able 1-7 lists the re gister v alues that need to be programmed for each input format. t able 1-7. register v alues for video input formats register bit ntsc-m ntsc-japan pal-b, d, g, h, i pal-m pal-n pal-n combination secam iform (0x01) xtsel 4:3 01 01 10 01 10 01 10 forma t 2:0 001 010 011 100 101 111 110 cropping: hdela y , vdela y , v active, crop 7:0 in all 5 registers set to desired crop- ping values in registers set to ntsc- m square pixel values set to desired cropping val- ues in regis- ters set to ntsc- m square pixel values set to p al-b, d, g, h, i square pixel values set to p al-b, d, g, h, i ccir values set to p al-b, d, g, h, i square pixel values hscale (0x08, 0x09) 15:0 0x02aa 0x02aa 0x033c 0x02ac 0x033c 0x00f8 0x033c adela y (0x18) 7:0 0x68 0x68 0x7f 0x68 0x7f 0x7f 0x7f bdela y (0x19) 7:0 0x5d 0x5d 0x72 0x5d 0x72 0x72 0xa0
18 1.0 functional description 1.6 y/c separation and chroma demodulation bt829b/827b v ideostr eam ii decoders d829bdsa 1.6 y/c separation and chroma demodulation y/c separation and chroma decoding is illustrated in figure 1-4 . bandpass and notch ? lters are implemented to separate the composite video stream. figure 1-5 displays the ? lter responses. the optional chroma comb ? lter is implemented in the v ertical scaling block. see the v ideo scaling, cropping, and t emporal deci- mation section in this chapter . figure 1-4. y/c separation and chroma demodulation for composite video notch filter band-p ass filter lo w-p ass filter lo w-p ass filter sin cos y u v composite figure 1-5. y/c separation filter responses ntsc p al/secam ntsc p al/secam luma notch filter f requency responses f or ntsc and p al/secam chroma band p ass filter f requency responses f or ntsc and p al/secam
v ideostr eam ii decoders 19 1.0 functional description bt829b/827b d829bdsa 1.6 y/c separation and chroma demodulation figure 1-6 schematically describes the ? ltering and scaling operations. in addition to the y/c separation and chroma demodulation illustrated in figure 1-4 , the bt829b also supports chrominance comb ? ltering as an optional ? ltering stage after chroma demodulation. the chroma demodulation generates baseband i and q (ntsc) or u and v (p al/secam) color dif ference signals. f or s-v ideo operation, the digitized luma data bypasses the y/c separation block completely , and the digitized chrominance is passed directly to the chroma demodulator . f or monochrome operation, the y/c separation block is also bypassed, and the saturation re gisters (sa t_u and sa t_v) are set to zero. figure 1-6. filtering and scaling operations note: zC1 refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. the coefficients are de- termined by ultralock and the scaling algorithm. c h r o m i n a n c e 1 2 - - - 1 2 - - - z 1 C + = l u m i n a n c e c d z 1 C + = v er tical scaler l u m i n a n c e a b z 1 C c z 2 C d z 3 C e z 4 C f z 5 C + + + + + = c h r o m i n a n c e g h z 1 C + = hor iz ontal scaler 6-t ap , 32-phase inter polation on-chip memor y and hor iz ontal scaling 2-t ap , 32-phase inter polation on-chip memor y and and hor iz ontal scaling chroma comb lo w-p ass filter y y c c optional hor iz ontal v er tical scaling luma comb (chroma comb) 3 mhz 1 4 - - - 1 2 z 1 C 1 z 2 C + + ( ) = 1 8 - - - 1 3 z 1 C 3 z 2 C 1 z 3 C + + + ( ) = 1 16 - - - - - - 1 4 z 1 C 6 z 2 C 4 z 3 C z 4 C + + + + ( ) = v er tical filter options v er tical scaling v er tical filter ing l u m i n a n c e 1 2 - - - 1 z 1 C + ( ) =
20 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa 1.7 video scaling, cropping, and t emporal decimation the bt829b pro vides three mechanisms to reduce the amount of video pix el data in its output stream: do wn-scaling, cropping, and temporal decimation. all three can be controlled independently . 1.7.1 horizontal and v ertical scaling the bt829b pro vides independent and arbitrary horizontal and v ertical do wn- scaling. the maximum scaling ratio is 16:1 in both x and y dimensions. the maximum v ertical scaling ratio is reduced from 16:1 when using frames, and to 8:1 when using ? elds. the dif ferent methods utilized for scaling luminance and chrominance are described in the follo wing sections. 1.7.2 luminance scaling the ? rst stage in horizontal luminance scaling is an optional pre-? lter which pro- vides the capability to reduce antialiasing artif acts. it is generally desirable to limit the bandwidth of the luminance spectrum prior to performing horizontal scaling because the scaling of high-frequenc y components may create image arti- f acts in the resized image. the optional lo w-pass ? lters sho wn in figure 1-7 reduce the horizontal high- frequenc y spectrum in the luminance signal. figure 1-8 and figure 1-9 illustrates the combined results of the optional lo w-pass ? lters, and the luma notch and 2x o v ersampling ? lter . figure 1-7. optional horizontal luma low-pass filter responses ntsc p al/secam icon qcif cif icon qcif cif
v ideostr eam ii decoders 21 1.0 functional description bt829b/827b d829bdsa 1.7 video scaling, cropping, and t emporal decimation the bt829b implements horizontal scaling through poly-phase interpolation. the bt829b uses 32 dif ferent phases to accurately interpolate the v alue of a pix el. this pro vides an ef fecti v e pix el jitter of less than 6 ns. in simple pix el- and line-dropping algorithms, non-inte ger scaling ratios intro- duce a step function in the video signal that ef fecti v ely introduces high-frequenc y spectral components. poly-phase interpolation accurately interpolates to the cor - rect pix el and line position pro viding more accurate information. this results in more aesthetically pleasing video as well as higher compression ratios in band- width limited applications. f or v ertical scaling, the bt829b uses a line store to implement four dif ferent ? ltering options. the ? lter characteristics are sho wn in figure 1-10 . the bt829b pro vides up to 5-tap ? ltering to ensure remo v al of aliasing artif acts. figure 1-11 displays the combined responses of the luma notch and 2x o v ersampling ? lters. figure 1-8. combined luma notch, 2x oversampling and optional low-pass filter response (ntsc) icon qcif cif icon qcif cif p ass band full spectr um figure 1-9. combined luma notch, 2x oversampling and optional low-pass filter response (p al/secam) icon qcif cif icon qcif cif p ass band full spectr um
22 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa figure 1-10. frequency responses for the four optional v ertical luma low-pass filters 2-tap 3-tap 4-tap 5-tap figure 1-11. combined luma notch and 2x oversampling filter response ntsc p al/secam
v ideostr eam ii decoders 23 1.0 functional description bt829b/827b d829bdsa 1.7 video scaling, cropping, and t emporal decimation 1.7.3 peaking the bt829b enables four dif ferent peaking le v els by programming the peak bit and hfil t bits in the scloop re gister . the ? lters are sho wn in figures 1-12 and 1-13 . figure 1-12. peaking filters hfil t = 00 hfil t = 11 hfil t = 10 hfil t = 01 hfil t = 00 hfil t = 10 hfil t = 11 hfil t = 01 enhanced resolution of p assband
24 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa the number of taps in the v ertical ? lter is set by the vtc re gister . the user may select tw o, three, four , or ? v e taps. the number of taps must be chosen in conjunction with the horizontal scale f actor to ensure that the needed data can ? t in the internal fifo (see the vfil t bits in the vtc re gister for limitations). as the scaling ratio is increased, the number of taps a v ailable for v ertical scaling is increased. in addition to lo w-pass ? ltering, v ertical interpolation is also emplo yed to minimize artif acts when scaling to non-inte ger scaling ratios. the BT827B emplo ys line dropping for v ertical scaling. figure 1-13. luma peaking filters with 2x oversampling filter and luma notch hfil t = 00 hfil t = 11 hfil t = 01 hfil t = 10 hfil t = 00 hfil t = 10 hfil t = 11 hfil t = 01 enhanced resolution of p assband
v ideostr eam ii decoders 25 1.0 functional description bt829b/827b d829bdsa 1.7 video scaling, cropping, and t emporal decimation 1.7.4 chrominance scaling a 2-tap, 32-phase interpolation ? lter is used for horizontal scaling of chromi- nance. v ertical scaling of chrominance is implemented through chrominance comb ? ltering using a line store, follo wed by simple decimation or line dropping. 1.7.5 scaling registers horizontal scaling ratio register (hscale) hscale is programmed with the horizontal scaling ratio. when outputting unscaled video (in ntsc), the bt829b will produce 910 pix els per line. this corresponds to the pix el rate at f clkx1 (4*fsc). this re gister is the control for scaling the video to the desired size. f or e xample, square pix el ntsc requires 780 samples-per -line, while ccir601 requires 858 samples-per -line. hscale_hi and hscale_lo are tw o 8-bit re g- isters that, when concatenated, form the 16-bit hscale re gister . the method belo w uses pix el ratios to determine the scaling ratio. the follo w- ing formula should be used to determine the scaling ratio to be entered into the 16-bit re gister: f or e xample, to scale p al/secam input to square pix el qcif , the total number of horizontal pix els is 236: an alternati v e method for determining the hscale v alue uses the ratio of the scaled acti v e re gion to the unscaled acti v e re gion as sho wn belo w: ntsc: hscale = [ ( 910/p desired ) C 1] * 4096 pal/secam: hscale = [ ( 1135/p desired ) C 1] * 4096 where: p desired = desired number of pix els per line of video, includ- ing active, sync and blanking. hscale = [ ( 1135/236 ) C 1 ] * 4096 = 15602 = 0x3cf2 ntsc: hscale = [ (754 / hactive) C 1] * 4096 pal/secam: hscale = [ (922 / hactive) C 1] * 4096 where: hactive = desired number of pix els per line of video, not including sync or blanking.
26 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa in this equation, the ha ctive v alue cannot be cropped; it represents the total acti v e re gion of the video line. this equation produces roughly the same result as using the full line length ratio sho wn in the ? rst e xample. ho we v er , due to trunca- tion, the hscale v alues determined using the acti v e pix el ratio will be slightly dif ferent than those obtained using the total line length pix el ratio. the v alues in t able 1-8 were calculated using the full line length ratio. t able 1-8. scaling ratios for popular formats using frequency v alues scaling ratio format total resolution (including sync and blanking interval) output resolution (active pixels) hscale register values vscale register values use both fields single field full resolution 1:1 ntsc sq pixel ntsc ccir601 p al ccir601 p al sq pixel 780 x 525 858 x 525 864 x 625 944 x 625 640 x 480 720 x 480 720 x 576 768 x 576 0x02ac 0x00f8 0x0504 0x033c 0x0000 0x0000 0x0000 0x0000 n/a n/a n/a n/a cif 2:1 ntsc sq pixel ntsc ccir601 p al ccir601 p al sq pixel 390 x 262 429 x 262 432 x 312 472 x 312 320 x 240 360 x 240 360 x 288 384 x 288 0x1555 0x11f0 0x1a09 0x1679 0x1e00 0x1e00 0x1e00 0x1e00 0x0000 0x0000 0x0000 0x0000 qcif 4:1 ntsc sq pixel ntsc ccir601 p al ccir601 p al sq pixel 195 x 131 214 x 131 216 x 156 236 x 156 160 x 120 180 x 120 180 x 144 192 x 144 0x3aaa 0x3409 0x4412 0x3cf2 0x1a00 0x1a00 0x1a00 0x1a00 0x1e00 0x1e00 0x1e00 0x1e00 icon 8:1 ntsc sq pixel ntsc ccir601 p al ccir601 p al sq pixel 97 x 65 107 x 65 108 x 78 118 x 78 80 x 60 90 x 60 90 x 72 96 x 72 0x861a 0x7813 0x9825 0x89e5 0x1200 0x1200 0x1200 0x1200 0x1a00 0x1a00 0x1a00 0x1a00 notes: 1. pal-mChscale and vscale register values should be the same for ntsc. 2. pal-n combinationChscale register values should be the same as for ccir resolution ntsc. vscale register values should be the same as for ccir resolution pal. 3. secamChscale and vscale register values should be the same as for pal.
v ideostr eam ii decoders 27 1.0 functional description bt829b/827b d829bdsa 1.7 video scaling, cropping, and t emporal decimation v er tical scaling ratio register (vscale) vscale is programmed with the v ertical scaling ratio. it de? nes the number of v ertical lines output by the bt829b. the follo wing formula should be used to determine the v alue to be entered into this 13-bit re gister . the loaded v alue is a tw o s-complement, ne g ati v e v alue. f or e xample, to scale p al/secam input to square pix el qcif , the total number of v ertical lines for p al square pix el is 156 (see t able 1-8 ). note: only the 13 least signi? cant bits (lsbs) of the vscale v alue are used. the ? v e lsbs of vscale_hi and the 8-bit vscale_lo re gister form the 13-bit vscale re gister . the three msbs of vscale_hi are used to control other functions. the user must tak e care not to alter the v alues of the three most signi? cant bits when writing a v ertical scaling v alue. the follo wing c-code fragment illustrates changing the v ertical scaling v alue: #define byte unsigned char #define word unsigned int #define vscale_hi 0x13 #define vscale_lo 0x14 byte readfrombt829b( byte regaddress ); void writetobt829b( byte regaddress, byte regvalue ); void setbt829bvscaling( word vscale ) { byte oldvscalemsbyte, newvscalemsbyte; /* get existing vscalemsbyte value from */ /* bt829b vscale_hi register */ oldvscalemsbyte = readfrombt829b( vscale_hi ); /* create a new vscalemsbyte, preserving top 3 bits */ newvscalemsbyte = (oldvscalemsbyte & 0xe0) | (vscale >> 8); /* send the new vscalemsbyte to the vscale_hi reg */ writetobt829b( vscale_hi, newvscalemsbyte ); /* send the new vscalelsbyte to the vscale_lo reg */ writetobt829b( vscale_lo, (byte) vscale ); } vscale = ( 0x10000 C { [ ( scaling_ratio ) C 1] * 512 } ) & 0x1fff vscale = ( 0x10000 C { [ ( 4/1 ) C1 ] * 512 } ) & 0x1fff = 0x1a00
28 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa if your tar get machine has suf ? cient memory to statically store the scaling v alues locally , the read operation can be eliminated. on v ertical scaling (when scaling belo w cif resolution) it may be useful to use a single ? eld as opposed to using both ? elds. using a single ? eld will ensure there are no inter -? eld motion artif acts on the scaled output. when performing single ? eld scaling, the v ertical scaling ratio will be twice as lar ge as when scal- ing with both ? elds. f or e xample, cif scaling from one ? eld does not require an y v ertical scaling, b ut when scaling from both ? elds, the scaling ratio is 50%. also, the non-interlaced bit should be reset when scaling from a single ? eld (int = 0 in the vscale_hi re gister). t able 1-8 lists scaling ratios for v arious video formats, and the re gister v alues required. 1.7.6 image cropping cropping enables the user to output an y subsection of the video image. the a ctive ? ag can be programmed to start and stop at an y position on the video frame as sho wn in figure 1-14 . the start of the acti v e area in the v ertical direction is referenced to vreset (be ginning of a ne w ? eld). in the horizontal direction it is referenced to hreset (be ginning of a ne w line). the dimensions of the acti v e video re gion are de? ned by hdela y , ha ctive, vdela y , and v a ctive. all four re gisters are 10-bit v alues. the tw o msbs of each re gister are contained in the cr op re gister , while the lo wer 8 bits are in the respecti v e hdela y_lo, ha ctive_lo, vdela y_lo, and v a ctive_lo re gisters. the v ertical and horizontal delay v alues determine the position of the cropped image within a frame while the horizontal and v ertical acti v e v alues set the pix el dimensions of the cropped image as illustrated in figure 1-14 . where: & = bitwise and | = bitwise or >> = bit shift, msb to lsb
v ideostr eam ii decoders 29 1.0 functional description bt829b/827b d829bdsa 1.7 video scaling, cropping, and t emporal decimation figure 1-14. effect of the cropping and active registers rising edge of vreset falling edge of hreset video frame hactive hdelay vdelay vactive video frame hactive hdelay vdelay vactive cropped image cropped image scaled to 1/2 size
30 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa 1.7.7 cropping registers horizontal dela y register (hdela y) hdela y is programmed with the delay between the f alling edge of hreset and the rising edge of a ctive. the count is programmed with respect to the scaled frequenc y clock. note: hdela y should al w ays be an e v en number . horizontal active register (ha ctive) ha ctive is programmed with the actual number of acti v e pix els per line of video. this is equi v alent to the number of scaled pix els that the bt829b should output on a line. f or e xample, if this re gister contained 90, and hscale w as programmed to do wn-scale by 4:1, then 90 acti v e pix els w ould be output. the 90 pix els w ould be a 4:1 scaled image of the 360 pix els (at clkx1) starting at count hdela y . ha ctive is restricted in the follo wing manner: hactive + hdelay total number of scaled pixels. f or e xample, in the ntsc square pix el format, there is a total of 780 pix els, including blanking, sync and acti v e re gions. therefore: hactive + hdelay 780. when scaled by 2:1 for cif , the total number of acti v e pix els is 390. there- fore: hactive +hdelay 390. the hdela y re gister is programmed with the number of scaled pix els between hreset and the ? rst acti v e pix el. because the front porch is de? ned as the distance between the last acti v e pix el and the ne xt horizontal sync, the video line can be considered in three components: hdela y , ha ctive, and the front porch. figure 1-15 illustrates the video signal re gions. figure 1-15. regions of the video signal hdela y ha ctive f ront p orch
v ideostr eam ii decoders 31 1.0 functional description bt829b/827b d829bdsa 1.7 video scaling, cropping, and t emporal decimation when cropping is not implemented, the number of clocks at the 4x sample rate (the clkx1 rate) in each of these re gions is as follo ws: the v alue for hdela y is calculated using the follo wing formula: hdelay = [(clkx1_hdelay / clkx1_hactive) * hactive] & 0x3fe clkx1_hdela y and clkx1_ha ctive are constant v alues, so the equa- tion becomes: ntsc: hdela y = [(135 / 754) * ha ctive] & 0x3fe p al/secam: hdela y = [(186 / 922) * ha ctive] & 0x3fe in this equation, the ha ctive v alue cannot be cropped. v er tical dela y register (vdela y) vdela y is programmed with the delay between the rising edge of vreset and the start of acti v e video lines. it deter - mines ho w man y lines to skip before initiating the a ctive signal. it is pro- grammed with the number of lines to skip at the be ginning of a frame. v er tical active register (v a ctive) v a ctive is programmed with the number of lines used in the v ertical scaling process. the actual number of v ertical lines output from the bt829b is equal to this re gister times the v ertical scaling ratio. if vscale is set to 0x1a00 (4:1), then the actual number of lines output is v a ctive/4. if vscale is set to 0x0000 (1:1), then v a ctive contains the actual number of v ertical lines output. note: it is important to note the dif ference between the implementation of the horizontal re gisters (hscale, hdela y , and ha ctive) and the v ertical re gisters (vscale, vdela y , and v a ctive). horizontally , hdela y and ha ctive are programmed with respect to the scaled pix els de? ned by hscale. v ertically , vdela y and v a ctive are programmed with respect to the number of lines before scaling (before vscale is applied). clkx1 front porch clkx1 hdelay clkx1 hactive clkx1 total ntsc 21 135 754 910 p al/secam 27 186 922 1135
32 1.0 functional description 1.7 video scaling, cropping, and t emporal decimation bt829b/827b v ideostr eam ii decoders d829bdsa 1.7.8 t emporal decimation t emporal decimation pro vides a solution for video synchronization during peri- ods when full frame rate cannot be supported due to bandwidth and system restrictions. f or e xample, when capturing li v e video for storage, system limitations such as hard disk transfer rates or system b us bandwidth may limit the frame capture rate. if these restrictions limit the frame rate to 15 frames per second, the bt829b s time scaling operation will enable the system to capture e v ery other frame instead of allo wing the hard disk timing restrictions to dictate which frame to capture. this maintains an e v en distrib ution of captured frames and alle viates the jerk y ef fects caused by systems that simply b urst in data when the bandwidth becomes a v ailable. the bt829b pro vides temporal decimation on either a ? eld or frame basis. the t emporal decimation tdec re gister is loaded with a v alue from 1 to 60 (ntsc) or 1 to 50 (p al/secam). this v alue is the number of ? elds or frames skipped by the chip during a sequence of 60 for ntsc or 50 for p al/secam. skipped ? elds and frames are considered inacti v e, which is indicated by the a ctive pin remaining lo w . consequently if qclk is programmed to depend on a ctive, qclk w ould become inacti v e as well. examples: when changing the programming in the temporal decimation re gister , 0x00 should be loaded ? rst, and then the decimation v alue. this will ensure that the decimation counter is reset to zero. if zero is not ? rst loaded, the decimation may start on an y ? eld or frame in the sequence of 60 (or 50 for p al/secam). on po wer -up, this preload is not necessary because the counter is reset internally . when decimating ? elds, the fld align bit in the tdec re gister can be pro- grammed to choose whether the decimation starts with an odd ? eld or an e v en ? eld. if the fld align bit is set to logical 0, the ? rst ? eld that is dropped during the decimation process will be an odd ? eld. con v ersely , setting the fld align bit to logical 1 causes the e v en ? eld to be dropped ? rst in the decimation process. tdec = 0x02 decimation is performed by frames. two frames are skipped per 60 frames of video, assuming ntsc decoding. frames 1C29 are output normally , then a ctive re- mains lo w for one frame. frames 30C59 are then output follo wed by another frame of inacti v e video. tdec = 0x9e decimation is performed by fields. thirty fields are output per 60 fields of video, assuming ntsc decoding. this v alue outputs e v ery other ? eld (e v ery odd ? eld) of video starting with field 1 in frame 1. tdec = 0x01 decimation is performed by frames. one frame is skipped per 50 frames of video, assuming pal/secam decoding. tdec = 0x00 decimation is not performed. full frame rate video is output by the bt829b.
v ideostr eam ii decoders 33 1.0 functional description bt829b/827b d829bdsa 1.8 video adjustments 1.8 video adjustments the bt829b pro vides programmable hue, contrast, saturation, and brightness. 1.8.1 the hue adjust register (hue) the hue adjust re gister is used to of fset the hue of the decoded signal. in ntsc, the hue of the video signal is de? ned as the phase of the subcarrier with reference to the b urst. the v alue programmed in this re gister is added or subtracted from the phase of the subcarrier , which ef fecti v ely changes the hue of the video. the hue can be shifted by 90 de grees. because of the nature of p al/secam encoding, hue adjustments cannot be made when decoding p al/secam. 1.8.2 the contrast adjust register (contrast) the contrast adjust re gister (also called the luma g ain) pro vides the ability to change the contrast from approximately 0 percent to 200 percent of the original v alue. the decoded luma v alue is multiplied by the 9-bit coef ? cient loaded into this re gister . 1.8.3 the saturation adjust registers (sa t_u, sa t_v) the saturation adjust re gisters are additional color adjustment re gisters. it is a multiplicati v e g ain of the u and v signals. the v alue programmed in these re gis- ters are the coef ? cients for the multiplication. the saturation range is from approximately 0 percent to 200 percent of the original v alue. 1.8.4 the brightness register (bright) the brightness re gister is simply an of fset for the decoded luma v alue. the pro- grammed v alue is added or subtracted from the original luma v alue which changes the brightness of the video output. the luma output is in the range of 0 to 255. brightness adjustment can be made o v er a range of C128 to +127.
34 1.0 functional description 1.9 bt829b vbi data output interface bt829b/827b v ideostr eam ii decoders d829bdsa 1.9 bt829b vbi data output interface 1.9.1 introduction a frame of video is composed of 525 lines for nstc and 625 for p al/secam. figure 1-16 illustrates an ntsc video frame in which there are a number of dis- tinct re gions. the video image or picture data is contained in the odd and even ? elds within lines 21C262 and lines 283C525, respecti v ely . each ? eld of video also contains a re gion for v ertical synchronization (lines 1C9 and 263C272) as well as a re gion which can contain non-video ancillary data (lines 10C20 and 273C282). w e will refer to these re gions which are between the v ertical synchro- nization re gion and the video picture re gion as the v ertical blanking interv al (vbi) portion of the video signal. 1.9.2 over view in the def ault con? guration of the bt829b, the vbi re gion of the video signal is treated the same w ay as the video image re gion of the signal. the bt829b will decode this signal as if it w as video. f or e xample, it will digitize at 8xfsc, deci- mate/? lter to a 4xfsc sample stream, color separate to deri v e luma and chroma component information, and interpolate for video synchronization and horizontal scaling. this process is sho wn in figure 1-17 . figure 1-16. regions of the video frame lines 1C9 lines 10C20 lines 21C262 lines 263C272 lines 273C282 lines 283C525 v er tical blanking inter v al video image region v er tical blanking inter v al video image region odd field ev en field v er tical synchronization region v er tical synchronization region figure 1-17. bt829b ycrcb 4:2:2 data path decimation filter y/c separ ation filter inter polation filter adc composite analog ycrcb 4:2:2 8xfsc 4xfsc
v ideostr eam ii decoders 35 1.0 functional description bt829b/827b d829bdsa 1.9 bt829b vbi data output interface the bt829b can be con? gured in a mode kno wn as vbi data pass through to enable capture of the vbi re gion ancillary data for later processing by softw are. in this mode the vbi re gion of the video signal is processed as follo ws: ? the analog composite video signal is digitized at 8*fsc (28.63636 mhz for ntsc and 35.46895 mhz for p al/secam). this 8-bit v alue repre- sents a number range from the bottom of sync tip to the peak of the com- posite video signal. ? the 8-bit data stream bypasses the decimation ? lter , y/c separation ? lters, and the interpolation ? lter (see figure 1-18 ). ? the bt829b pro vides the option to pack the 8*fsc data stream into a 2- byte-wide stream at 4*fsc before outputting it to the vd[15:0] data pins, or it can simply be output as an 8-bit 8*fsc data stream on pins vd[15:8]. in the pack ed format, the ? rst byte of each pair on a 4*fsc clock c ycle is mapped to vd[15:8] and the second byte to vd[7:0] with vd[7] and vd[15] being the msbs. the bt829b uses the same 16-pin data port for vbi data and ycrcb 4:2:2 image data. the byte pair ordering is programmable. ? the vbi datastream is not pipeline-delayed to match the ycrcb 4:2:2 image output data with respect to horizontal timing (i.e., v alid vbi data will be output earlier than ycrcb 4:2:2 relati v e to the bt829b hreset signal). ? a lar ger number of pix els per line are generated in vbi output mode than in ycrcb 4:2:2 output mode. the do wnstream video processor must be capable of dealing with a v arying number of pix els per line in order to cap- ture vbi data, as well as ycrcb 4:2:2 data from the same frame. ? the follo wing pins may be used to implement this solution: vd[15:0], v a ctive, ha ctive, d v alid, vreset , hreset , clkx1, clkx2, and qclk. this should allo w the do wnstream video processor to load the vbi data and the ycrcb 4:2:2 data correctly . ? because the 8*fsc data stream does not pass through the interpolation ? l- ter , the sample stream is not lock ed/synchronized to the horizontal sync timing. the only implication of this is that the sample locations on each line are not correlated v ertically . figure 1-18. bt829b vbi data path decimation filter y/c separ ation filter inter polation filter adc composite analog vbi data 8xfsc 4xfsc p ac k decimation filter y/c separ ation filter inter polation filter adc composite analog vbi data 8xfsc 8 16 8
36 1.0 functional description 1.9 bt829b vbi data output interface bt829b/827b v ideostr eam ii decoders d829bdsa 1.9.3 functional description there are three modes of operation for the bt829b vbi data pass-through feature: 1 vbi data p ass through disabled. this is the def ault mode of operation for the bt829b during which the de vice decodes composite video and gener - ates a ycrcb 4:2:2 data stream. 2 vbi line output mode. the de vice outputs un? ltered 8*fsc data only dur - ing the v ertical interv al which is de? ned by the v a ctive output signal pro vided by the bt829b. data is output between the trailing edge of the vreset signal and the leading edge of v a ctive. when v a ctive is high, the bt829b is outputting standard ycrcb 4:2:2 data. this mode of operation is intended to be used to enable capture of vbi lines containing ancillary data in addition to processing normal ycrcb 4:2:2 video image data. 3 vbi frame output mode. in this mode the bt829b treats e v ery line in the video signal as if it were a v ertical interv al line and outputs only the un? l- tered 8*fsc data on e v ery line (i.e., it does not output an y image data). this mode of operation is designed for use in still-frame capture/processing applications. 1.9.4 vbi line output mode the vbi line output mode is enabled via the vbien bit in the vtc re gister (0x1b). when enabled, the vbi data is output during the vbi acti v e period. the vbi horizontal acti v e period is de? ned as the interv al between consecuti v e bt829b hreset signals. speci? cally , it starts at a point one clkx1 interv al after the trailing edge of the ? rst hreset and ends with the leading edge of the follo wing hreset . this interv al is coincident with the ha ctive signal as indicated in figure 1-19 . d v alid is al w ays at a logical 1 during vbi. also, qclk is operating contin- uously at clkx1 or clkx2 rate during vbi. v alid vbi data is a v ailable one clkx1 (or qclk) interv al after the trailing edge of hreset . when the bt829b is con? gured in vbi line output mode, it is generating in v alid data outside of the vbi horizontal acti v e period. in standard ycrcb output mode, the horizontal acti v e period starts at a time point delayed from the leading edge of hreset as de? ned by the v alue programmed in the hdela y re gister . figure 1-19. vbi line output mode t iming hreset ha ctive vd[15:0] vbi data
v ideostr eam ii decoders 37 1.0 functional description bt829b/827b d829bdsa 1.9 bt829b vbi data output interface the vbi data sample stream which is output during the vbi horizontal acti v e period represents an 8*fsc sampled v ersion of the analog video signal starting in the vicinity of the subcarrier b urst and ending after the leading edge of the hori- zontal synchronization pulse as illustrated in figure 1-20 . the number of vbi data samples generated on each line may v ary depending on the stability of the analog composite video signal input to the bt829b. the bt829b will generate 845 16-bit vbi data w ords for ntsc and 1,070 16-bit vbi data w ords for p al/secam on each vbi line at a clkx1 rate, assuming a nom- inal or ideal video input signal (i.e., the analog video signal has a stable horizontal time base). this is also equi v alent to 1,690 8-bit vbi data samples for ntsc and 2,140 8-bit vbi data samples for p al/secam. these v alues can de viate from the nominal depending on the actual line length of the analog video signal. the vbi v ertical acti v e period is de? ned as the period between the trailing edge of the bt829b vreset signal and the leading edge of v a ctive. note: the e xtent of the vbi v ertical acti v e re gion can be controlled by setting dif ferent v alues in the vdela y re gister . this pro vides the ? e xibility to con? gure the vbi v ertical acti v e re gion as an y group of consecuti v e lines starting with line 10 and e xtending to the line number set by the equi v alent line count v alue in the vdela y re gister (i.e., the vbi v ertical acti v e re gion can be e xtended into the video image re gion of the video signal). the vbi horizontal acti v e period starts with the trailing edge of an hreset ; therefore, if a rising edge of vreset occurs after the horizontal acti v e period has already started, the vbi acti v e period starts on the follo wing line. the ha ctive pin is held at a logical 1 during the vbi horizontal acti v e period. d v alid is held high during both the vbi horizontal acti v e and horizontal inacti v e periods (i.e., it is held high during the whole vbi scan line.) these relationships are illustrated in figure 1-21 . figure 1-20. vbi sample region extent of analog signal captured in vbi samples
38 1.0 functional description 1.9 bt829b vbi data output interface bt829b/827b v ideostr eam ii decoders d829bdsa figure 1-21. location of vbi data vreset hreset ha ctive v a ctive d v alid vd[15:0] vreset hreset ha ctive v a ctive d v alid vd[15:0] vbi data vbi data vbi data vbi data ycrcb data ycrcb data vbi activ e region vbi activ e region ev en field odd field in v alid data in v alid data vbi data vbi data
v ideostr eam ii decoders 39 1.0 functional description bt829b/827b d829bdsa 1.9 bt829b vbi data output interface the bt829b can pro vide vbi data in all the pix el port output con? gurations (i.e., 16-bit spi, 8-bit spi, and bytestream modes). the range of the vbi data can be controlled with the range bit in the oform re gister (0x12). it is necessary to limit the range of vbi data for bytestream output mode. there must be a video signal present on the bt829b analog input as de? ned by the status of the vpres bit in the st a tus re gister in order for the bt829b to generate vbi data. if the status of the vpres bit re? ects no analog input, then the bt829b generates ycrcb data to create a ? at blue ? eld image. the order in which the vbi data is presented on the output pins is programma- ble. setting the vbifmt bit in the vtc re gister to a logical 0 places the nth data sample on vd[15:8] and the nth+1 sample on vd[7:0]. setting vbifmt to a log- ical 1, logical 0 re v erses the abo v e. similarly , in bytestream and 8-bit output modes, setting vbifmt = 0 generates a vbi sample stream with an ordering sequence of n+1, n, n+3, n+2, n+5, n+4, etc. setting vbifmt = 1 for bytestream/8-bit output generates an n, n+1, n+2, n+3, etc. sequence as sho wn in figure 1-22 . a video processor/controller must be able to do the follo wing to capture vbi data output by the bt829b: ? k eep track of the line count in order to select a limited number of speci? c lines for processing of vbi data. ? handle data type transitioning on the ? y from the v ertical interv al to the acti v e video image re gion. f or e xample, during the v ertical interv al with vbi data pass through enabled, it must grab e v ery byte pair while ha c- tive is high using the 4*fsc clock or qclk. ho we v er , when the data stream transitions into ycrcb 4:2:2 data mode with v a ctive going high, the video processor must interpret the d v alid signal (or use qclk for the data load clock) from the bt829b for pix el quali? cation and use only v alid pix el c ycles to load image data (def ault bt829b operation). ? handle a lar ge and v arying number of horizontal pix els per line in the vbi re gion as compared to the acti v e image re gion. figure 1-22. vbi sample ordering vd[15:8] vd[7:0] clkx1 vd[15:8] clkx2 n n+2 n+1 n+3 n n+2 n+1 n+3 16-bit spi mode (vbifmt = 0) 8-bit spi mode (vbifmt = 1)
40 1.0 functional description 1.9 bt829b vbi data output interface bt829b/827b v ideostr eam ii decoders d829bdsa 1.9.5 vbi frame output mode in vbi frame output mode, the bt829b is generating vbi data all the time (i.e., there is no vbi acti v e interv al). in essence, the bt829b is acting as an adc continuously sampling the entire video signal at 8*fsc. the bt829b generates hreset , vreset and field timing signals in addition to the vbi data, b ut the d v alid, ha ctive, and v a ctive signals are all held high during vbi frame output operation. the beha vior of the hreset , vreset , and field timing signals is the same as normal ycrcb 4:2:2 output operation. the hreset , vreset , and field timing signals can be used by the video processor to detect the be ginning of a video frame/? eld, at which point it can start to capture a full frame/? eld of vbi data. the number of vbi data samples generated on each line may v ary depending on the stability of the analog composite video signal input to the bt829b. the bt829b will generate 910 16-bit vbi data w ords for ntsc and 1,135 16-bit vbi data w ords for p al/secam for each line of analog video input at a clkx1 rate, assuming a nominal or ideal video input signal (i.e., analog video signal has a sta- ble horizontal time base). this is also equi v alent to 1,820 8-bit vbi data samples for ntsc and, 270 8-bit vbi data samples for p al/secam for each line of ana- log video input. these v alues can de viate from the nominal depending on the actual line length of the analog video signal. vbi frame output mode is enabled via the vbifrm bit in the oform re gis- ter . the output byte ordering may be controlled by the vbifmt bit as described for vbi line output mode. if both vbi line output and vbi frame output modes are enabled at the same time, the vbi frame output mode tak es precedence. the vbi data range in vbi frame output mode can be controlled using the range bit in the oform re gister , and a video signal must be present on the bt829b ana- log input for this mode to operate as de? ned by the status of the vpres bit in the st a tus re gister (0x00).
v ideostr eam ii decoders 41 1.0 functional description bt829b/827b d829bdsa 1.10 closed captioning and extended data ser vices decoding 1.10 closed captioning and extended data ser vices decoding in a system capable of capturing closed captioning and extended data services adhering to the eia-608 standard, 2 bytes of information are presented to the video decoder on line 21 (odd ? eld) for cc and an additional tw o bytes are pre- sented on line 284 (e v en ? eld) for eds. the data presented to the video decoder is an analog signal on the composite video input. the signal contains information identifying it as the cc/eds data and is follo wed by a control code and 2 bytes of digital information transmitted by the analog signal. f or the purposes of cc/eds, only the luma component of the video signal is rele v ant. therefore, the composite signal goes through the dec- imation and y/c separation blocks of the bt829b before an y cc/eds decoding tak es place. see figure 1-23 for a representation of this procedure. the bt829b can be programmed to decode cc/eds data via the correspond- ing bits in the extended data services/closed caption status re gister (cc_st a tus;0x1c). the cc and eds are independent and the video decoder may capture one or both in a gi v en frame. the cc/eds signal is displayed in figure 1-24 . in cc/eds decode mode, once bt829b has detected that line 21 of the ? eld is being displayed, the decoder looks for the clock run-in signal. if the clock run-in signal is present and the correct start code (001) is recognized by bt829b, then the cc/eds data capture commences. each of the 2 bytes of data transmitted to the video decoder per ? eld contains a 7-bit ascii code and a parity bit. the con v ention for cc/eds data is odd parity . figure 1-23. cc/eds data processing path decimation filter y/c separ ation filter inter polation filter adc composite analog ycrcb 4:2:2 cc/eds decoder cc/eds fifo cc_data register cc_status register i 2 c i 2 c luma figure 1-24. cc/eds incoming signal s1 s2 s3 b0 b1 b2 b3 b4 b5 b6 p1 b0 b1 b2 b3 b4 b5 b6 p2 star t bits char acter one char acter t w o cloc k run-in color hsync burst 50 25 0 C40 ire
42 1.0 functional description 1.10 closed captioning and extended data ser vices decoding bt829b/827b v ideostr eam ii decoders d829bdsa the bt829b pro vides a 16 x 10 location fifo for storing cc/eds data. once the video decoder detects the start signal in the cc/eds signal, it captures the lo w byte of cc/eds data ? rst and checks to see if the fifo is full. if the fifo is not full, then the data is stored in the fifo, and is a v ailable to the user through the cc_d a t a re gister (0x1d). the high byte of cc/eds data is captured ne xt and placed in the fifo. upon being placed in the 10-bit fifo, tw o additional bits are attached to the cc/eds data byte by bt829b s cc/eds decoder . these tw o bits indicate whether the gi v en byte stored in the fifo corresponds to cc or eds data and whether it is the high or lo w byte of cc/eds. these tw o bits are a v ail- able to the user through the cc_st a tus re gister bits cc_eds and lo_hi, respecti v ely . the parity bit is stored in the fifo as sho wn in figure 1-25 . additionally , the bt829b stores the results of the parity check in the p arity_err bit in the cc_st a tus re gister . the 16-location fifo can hold eight lines w orth of cc/eds data, at tw o bytes per line. initially when the fifo is empty , the d a bit in the cc_st a tus re gister (0x1c) is set lo w and indicates that no data is a v ailable in the fifo. subse- quently , when data has been stored in the fifo, the d a bit is set to logical high. once the fifo is half full, the cc_v alid interrupts pin signals to the system that the fifo contents should be read in the near future. the cc_v alid pin is enabled via a bit in the cc_st a tus re gister (0x1c). the system controller can then poll the cc_v alid bit in the st a tus re gister (0x00) to ensure that it w as the bt829b that initiated the cc_v alid interrupt. this bit can also be used in applications where the cc_v alid pin is disabled by the user . figure 1-25. closed captioning/extended data ser vices fifo location 0 location 1 location 15 9 8 7 6 0 msb lsb ... ... 7-bit ascii code a v ailab le through cc_d a t a register p ar ity bit a v ailab le through cc_d a t a register lo_hi a v ailab le through cc_st a tus register cc_eds a v ailab le through cc_st a tus register
v ideostr eam ii decoders 43 1.0 functional description bt829b/827b d829bdsa 1.10 closed captioning and extended data ser vices decoding when the ? rst byte of cc/eds data is decoded and stored in the fifo, the data is immediately placed in the cc_d a t a and cc_st a tus re gisters and is a v ailable to be read. once the data is read from the cc_d a t a re gister , the infor - mation in the ne xt location of the fifo is placed in the cc_d a t a and cc_st a tus re gisters. if the controller in the system ignores the bt829b cc_v alid interrupts pin for a suf ? ciently long period of time, then the cc/eds fifo will become full and the bt829b will not be able to write additional data to the fifo. an y incoming bytes of data will be lost and an o v er? o w condition will occur; bit or in the cc_st a tus re gister will be set to a logical 1. the system may clear the o v er? o w condition by reading the cc/eds data and creating space in the fifo for ne w information. as a result, the o v er? o w bit is reset to a logical 0. there will routinely be asynchronous reads and writes to the cc/eds fifo. the writes will be from the cc/eds circuitry and the reads will occur as the sys- tem controller reads the cc/eds data from bt829b. these reads and writes will sometimes occur simultaneously , and the bt829b is designed to gi v e priority to the read operations. in the case where the cc_d a t a re gister data is speci? cally being read to clear an o v er? o w condition, the simultaneous occurrence of a read and a write will not cause the o v er? o w bit to be reset, e v en though the read has priority . an additional read must be made to the cc_d a t a re gister in order to clear the o v er? o w condition. as al w ays, the write data will be lost while the fifo is in o v er? o w condition. the fifo is reset when both cc and eds bits are disabled in the cc_st a tus re gister; an y data in the fifo is lost. 1.10.1 automatic chrominance gain control the automatic chrominance gain control (a cgc) compensates for reduced chrominance and color -b urst amplitude. this can be caused by high-frequenc y loss in cabling. here, the color -b urst amplitude is calculated and compared to nominal. the color -dif ference signals are then increased or decreased in ampli- tude according to the color -b urst amplitude dif ference from nominal. the maxi- mum amount of chrominance g ain is 0.5C2 times the original amplitude. this compensation coef ? cient is then multiplied by the v alue in the saturation adjust re gister for a total chrominance g ain range of 0C2 times the original signal. auto- matic chrominance g ain control may be disabled by setting the a cgc bit in the scloop re gister to a logical 0. 1.10.2 low color detection and removal if a color b urst of 25 percent (ntsc) or 35 percent (p al/secam) or less of the nominal amplitude is detected for 127 consecuti v e scan lines, the color -dif ference signals u and v are set to zero. when the lo w color detection is acti v e, the reduced chrominance signal is still separated from the composite signal to gener - ate the luminance portion of the signal. the resulting cr and cb v alues are 128. output of the chrominance signal is re-enabled when a color b urst of 43 percent (ntsc) or 60 percent (p al/secam) or greater of nominal amplitude is detected for 127 consecuti v e scan lines. lo w color detection and remo v al may be disabled by setting the ckill bit in the scloop re gister (0x10) to a logical 0.
44 1.0 functional description 1.10 closed captioning and extended data ser vices decoding bt829b/827b v ideostr eam ii decoders d829bdsa 1.10.3 coring the bt829b video decoder can perform a coring function, in which it forces all v alues belo w a programmed le v el to be zero. this is useful because the human e ye is more sensiti v e to v ariations in black images. by taking near -black images and turning them into black, the image appears clearer to the e ye. f our coring v alues can be selected by the output f ormat re gister (oform; 0x12): 0, 8, 16, or 32 abo v e black. if the total luminance le v el is belo w the selected limit, the luminance signal is truncated to the black v alue. if the luma range is limited (i.e., black is 16), then the coring circuitry automatically tak es this into account and references the appropriate v alue for black. this is illustrated in figure 1-26 . figure 1-26. coring map 32 16 8 0 32 16 8 0 calculated luma v alue output luma v alue
45 d829bdsa 2.0 electrical interfaces 2.1 input interface 2.1.1 analog signal selection the bt829b/827b contains an on-chip 4:1 mux. f or the bt829b and BT827B, this multiple x er can be used to switch between four composite sources or three composite sources and one s-v ideo source. in the ? rst con? guration, connect the inputs of the multiple x er (mux[0], mux[1], mux[2], and mux[3]) to the four composite sources. in the second con? guration, connect three inputs to the com- posite sources and the other input to the luma component of the s-v ideo connec- tor . in both con? gurations the output of the multiple x er (muxout) should be connected to the input to the luma a/d (yin) and the input to the sync detection circuitry (syncdet) through a optional 0.1 m f capacitor (to maintain compati- bility with the bt829/827). when implementing s-v ideo, the input to the chroma a/d (cin) should be connected to the chroma signal of the s-v ideo connector . use of the multiple x er is not a requirement for operation. if digitization of only one video source is required, the source may be connected directly to yin. 2.1.2 multiplexer considerations the multiple x er is not a break-before-mak e design. therefore, during the multi- ple x er switching time it is possible for the input video signals to be momentarily connected together through the equi v alent of 200 w . the multiple x ers cannot be switched on a real-time pix el-by-pix el basis.
46 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.1.3 autodetection of ntsc or p al/secam video if the bt829b is con? gured to decode both ntsc and p al/secam, the bt829b can be programmed to automatically detect which format is being input to the chip. autodetection will select the proper clock source for the detected format. if ntsc/p alCm is detected, xt al0 is selected. if p al/secam is detected, xt al1 is selected. f or p al-n combination the user must manually select the xt al0 crystal. full control of the decoding con? guration can be programmed by writing to the input f ormat re gister (0x01). the bt829b determines the video source input to the chip by counting the number of lines in a frame. bit numl indicates the result in the st a tus re gis- ter . based on this bit, the format of the video is determined, and xt0 or xt1 is selected for the clock source. automatic format detection will select the clock source, b ut it will not program the required re gisters. the scaling and cropping re gisters (vscale, hscale, vdela y , hdela y , v a ctive, and ha ctive), as well as the b urst delay and a gc delay re gisters (bdela y and adela y) must be programmed accordingly . 2.1.4 flash a/d converters the bt829b and BT827B use tw o on-chip ? ash a/d con v erters to digitize the video signals. yref+, cref+, yrefC, and crefC are the respecti v e top and bottom of the internal resistor ladder . the input video is al w ays a c-coupled to the decoder . crefC and yrefC are connected to analog ground. the v oltage le v els for yref+ and cref+ are controlled by the g ain control circuitry . if the input video momentarily e xceeds the corresponding ref+ v oltage, it is indicated by lof and cof in the st a tus re gister . 2.1.5 a/d clamping an internally generated clamp control signal is used to clamp the inputs of the a/d con v erter for dc restoration of the video signals. clamping for both the yin and cin analog inputs occurs within the horizontal sync tip. the yin input is al w ays restored to ground while the cin input is al w ays restored to clevel. clevel can be set with an optional e xternal resistor netw ork so that it is biased to the midpoint between crefC and cref+. this ensures backw ard compatibil- ity with the bt819a/7a/5a, b ut is not required for the bt829b/827b. external clamping is not required because internal clamping is automatically performed. 2.1.6 power -up operation upon po wer -up, the status of the bt829b s re gisters is indeterminate. the rst signal must be asserted to set the re gister bits to their def ault v alues. the bt829b de vice def aults to ntsc-m format upon reset. if pin 85 (oepole) is tied to a logical high on po wer -up and the rst signal is asserted, then the video pix el b us, sync signals, and output clocks will be three-stated.
47 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.1.7 automatic gain controls (agc) the refout , cref+, and yref+ pins should be connected together as sho wn in figure 2-1 . in this con? guration, the bt829b controls the v oltage for the top of the reference ladder for each a/d. the automatic g ain control adjusts the yref+ and cref+ v oltage le v els until the back porch of the y -video input generates a digital code 0x38 from the a/d. if the video being digitized has a non-standard sync height to video height ratio, the digital code used for a gc may be changed by programming the adc interf ace re gister (0x1a). figure 2-2 illustrates bt829b e xternal circuitry with reduced passi v e components.
48 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa figure 2-1. bt829b t ypical external circuitr y with third overtone cr ystal oscillators (5 v vdd) mux2 mux3 cin muxout yin syncdet crefC yrefC clevel refout yref+ cref+ 0.1 m f xt0i xt0o 2.7 m h 22 pf 33 pf 0.1 m f 28.63636 xt1i xt1o 2.2 m h 22 pf 33 pf 0.1 m f 35.46895 jt a g i 2 c video timing antialiasing filter 75 w t er mination a c-coupling capacitor 1 m w 1 m w mhz mhz analog ground digital ground 0.1 m f v aa vpos a gccap vneg 75 w 1.0 m f mux0 75 w 330 pf 330 pf 1.0 m f 3.3 m h mux(0C2) 75 w 1.0 m f 75 w 1.0 m f 75 w 0.1 m f optional ccv alid vdd 100 k w 75 w 1.0 m f mux1 v aa 0.1 m f
49 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa figure 2-2. bt829b t ypical external circuitr y with third overtone cr ystal oscillators (3.3v vddo) mux2 mux3 cin muxout yin syncdet crefC yrefC clevel refout yref+ cref+ 0.1 m f xt0i xt0o 2.7 m h 22 pf 0.1 m f 28.63636 xt1i xt1o 22 pf 22 p f 35.46895 jt a g i 2 c video timing antialiasing filter 75 w t er mination a c-coupling capacitor 1 m w 1 m w mhz mhz analog ground digital ground 0.1 m f v aa vpos a gccap vneg 75 w 1.0 m f mux0 75 w 330 pf 330 pf 1.0 m f 3.3 m h mux(0C2) 75 w 1.0 m f 75 w 1.0 m f 75 w 0.1 m f optional ccv alid vdd 100 k w 75 w 1.0 m f mux1 v aa 0.1 m f 68 pf 2.7 m h 100 pf
50 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.1.8 cr ystal inputs and clock generation the bt829b has tw o pairs of pins: xt0i/xt0o and xt1i/xt1o. the y are used to input a clock source. if both ntsc and p al video are being digitized, both clock inputs must be implemented. the xt0 port is used to decode ntsc video and must be con? gured with a 28.63636 mhz source. the xt1 port is used to decode p al video and must be con? gured with a 35.46895 mhz source. if the bt829b is con? gured to decode either ntsc or p al, b ut not both, then only one clock source must be pro vided to the chip and it must be connected to the xt0i/xt0o port. if a crystal input is not used, the crystal ampli? ers are internally shut do wn to sa v e po wer . crystals are speci? ed as follo ws: ? 28.636363 mhz or 35.468950 mhz ? third o v ertone ? p arallel resonant ? 30 pf load capacitance ? 50 ppm ? series resistance 40 w or less the follo wing crystals are recommended for use with the bt829b: 1 standard crystal (818) 443-2121 2b ak28m636363gle30a 2b ak35m468950gle30a 2 ged (619) 591-4170 pkhc49-28.63636-.030-005-40r, 3rd o v ertone crystal pkhc49-35.46895-.030-005-40r, 3rd o v ertone crystal 3 m-t ron (800) 762-8800 mp-1 28.63636, 3rd o v ertone crystal mp-1 35.46895, 3rd o v ertone crystal 4 monitor (619) 433-4510 mm49x3c3a-28.63636, 3rd o v ertone crystal mm49x3c3a-35.46895, 3rd o v ertone crystal 5 cts (815) 786-8411 r3b55a30-28.63636, 3rd o v ertone crystal r3b55a30-35.46895, 3rd o v ertone crystal 6 f ox (813) 693-0099 hc49u-28.63636, 3rd o v ertone crystal hc49u-35.46895, 3rd o v ertone crystal the tw o clock sources may be con? gured using single-ended oscillators, fun- damental cut crystals, or third o v ertone mode crystals, with parallel resonant. if single-ended oscillators are used, the y must be connected to xt0i and xt1i. figure 2-3 sho ws the clock source options and circuit requirements.
51 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa the clock source tolerance should be 50 ppm or less, b ut 100 ppm is accept- able. de vices that output cmos v oltage le v els are required. the load capacitance in the crystal con? gurations may v ary , depending on the magnitude of board par - asitic capacitance. the bt829b is dynamic; to ensure proper operation, the clocks must al w ays be running with a minimum frequenc y of 28.64 mhz. the clkx1 and clkx2 outputs from the bt829b are generated from xt0 and xt1 clock sources. clkx2 operates at the crystal frequenc y (8xfsc), while clkx1 operates at half the crystal frequenc y (4xfsc). when the bt829b is run in the 3.3 v digital i/o mode using third o v ertone crystals, the circuit sho wn in figure 2-3 must be used. when the bt829b is run in normal 5 v mode using third o v ertone crystals, the circuit sho wn in figure 2-4 must be used.
52 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa figure 2-3. clock options (3.3 v vdd) p al/secam thir d over tone mode cr ystal oscillator 22 pf xt1i xt1o 35.46895 mhz ntsc thir d over tone mode cr ystal oscillator 22 pf 22 pf xt0i xt0o 28.63636 mhz xt1i xt1o xt0i xt0o 47 pf 47 pf 28.63636 mhz 47 pf 47 pf 35.46895 mhz p al/secam fundamental cr ystal oscillator ntsc fundamental cr ystal oscillator 1 m w 1 m w 1 m w 1 m w xt1i xt1o xt0i xt0o p al/secam single-ended oscillator ntsc single-ended oscillator osc osc 28.63636 mhz 35.46895 mhz 2.7 m h 100 pf 2.7 m h 68 pf 22 pf
53 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa figure 2-4. clock options (5 v vdd) p al/secam thir d over tone mode cr ystal oscillator 2.2 m h 33 pf 0.1 m f 22 pf xt1i xt1o 35.46895 mhz ntsc thir d over tone mode cr ystal oscillator 2.7 m h 33 pf 0.1 m f 22 pf xt0i xt0o 28.63636 mhz xt1i xt1o xt0i xt0o 47 pf 47 pf 28.63636 mhz 47 pf 47 pf 35.46895 mhz p al/secam fundamental cr ystal oscillator ntsc fundamental cr ystal oscillator 1 m w 1 m w 1 m w 1 m w xt1i xt1o xt0i xt0o p al/secam single-ended oscillator ntsc single-ended oscillator osc osc 28.63636 mhz 35.46895 mhz
54 2.0 electrical interfaces 2.1 input interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.1.9 2x oversampling and input filtering t o a v oid aliasing artif acts, digitized video needs to be band-limited. because the bt829b samples at clkx2 (8xfscmore than twice the normal rate), no ? ltering is required at the input to the a/ds. the analog video needs to be band-limited to 14.32 mhz in ntsc and 17.73 mhz in p al/secam mode. normal video signals do not require additional e xternal ? ltering. ho we v er , if noise or other signal content is e xpected abo v e these frequencies, the optional antialiasing ? lter sho wn in figure 2-1 may be included in the input signal path. after digitization, the samples are digitally lo w-pass ? ltered and then decimated to clkx1. the response of the digital lo w-pass ? lter is sho wn in figure 2-5 . the digital lo w-pass ? lter pro vides the digital bandwidth reduction to limit the video to 6 mhz. figure 2-5. luma and chroma 2x oversampling filter ntsc p al/secam ntsc p al/secam
55 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.2 output interface 2.2.1 output interfaces the bt829b supports a synchronous pix el interf ace (spi). spi can support 8-bit or 16-bit ycrcb 4:2:2 data streams. bt829b outputs all pix el and control data synchronous with clkx1 (16-bit mode), or clkx2 (8-bit mode). ev ents such as hreset and vreset may also be encoded as control codes in the data stream to enable a reduced pin interf ace (bytestream ? ). mode selections are controlled by the state of the oform re gister (0x12). figure 2-6 sho ws a diagram summarizing the dif ferent operating modes. on po wer -up, the bt829b automatically initializes to spi mode 1, 16 bits wide. figure 2-6. output mode summar y spi 8-bit 16-bit 8-bit 16-bit p ar allel control (spi mode 1) coded control (spi mode 2) (bytestream)
56 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.2.2 ycrcb pixel stream format, spi mode, 8- and 16-bit formats when the output is con? gured for an 8-bit pix el interf ace, the data is output on pins vd[15:8]. eight bits of chrominance data precede 8 bits of luminance data for each pix el. ne w pix el data is output on the pix el port after each rising edge of clkx2. when the output is con? gured for the 16-bit pix el interf ace, the luminance data is output on vd[15:8], and the chrominance data is output on vd[7:0]. in 16-bit mode, the data is output with respect to clkx1. see t able 2-1 for a summary of output interf ace con? gurations. the ycrcb 4:2:2 pix el stream follo ws the ccir recommendation, as illustrated in figure 2-7 . t able 2-1. pixel/pin map 16-bit pixel interface pin name vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 data bit y7 y6 y5 y4 y3 y2 y1 y0 crcb7 crcb6 crcb5 crcb4 crcb3 crcb2 crcb1 crcb0 8-bit pixel interface pin name vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 y -data bit y7 y6 y5 y4 y3 y2 y1 y0 c-data bit crcb7 crcb6 crcb5 crcb4 crcb3 crcb2 crcb1 crcb0 figure 2-7. ycrcb 4:2:2 pixel stream format (spi mode, 8- and 16-bits) 8-bit pix el interf ace clkx1 16-bit pix el interf ace cb0 y0 cr0 y1 cb2 y2 cr2 y3 cb0 cr0 y0 y1 cb2 cr2 y2 y3 vd[15:8] vd[15:8] vd[7:0] clkx2
57 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.2.3 synchronous pixel interface (spi mode 1) upon reset, the bt829b initializes to the spi output, mode 1 (spi-1). in this mode, bt829b outputs all horizontal and v ertical blanking interv al pix els, in addi- tion to the acti v e pix els synchronous with clkx1 (16-bit mode), or clkx2 (8-bit mode). figure 2-8 illustrates spi-1 for the bt829b. the basic timing relationships remain the same for 16-bit or 8-bit modes. the 16-bit mode uses clkx1 as the reference. the 8-bit mode uses clkx2. figure 2-9 sho ws the video timing for spi mode 1. figure 2-8. bt829b/827b synchronous pixel interface, mode 1 (spi-1) hreset vreset a ctive d v alid cbfla g field vd[15:0] oe 16 clkx1 (4*fsc) bt829b clkx2 (8*fsc) qclk figure 2-9. basic t iming relationships for spi mode 1 vd[15:0] d v alid a ctive clkx1 or clkx2 qclk cbfla g
58 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.2.4 synchronous pixel interface (spi mode 2, bytestream) in spi mode 2, the bt829b encodes all video timing control signals onto the pix el data b us. bytestream is the 8-bit v ersion of this con? guration. because all timing data is included on the data b us, a complete interf ace to a video controller can be implemented in only nine pins: one for clk x 2, and eight for data. when using coded control, the range bit and the code bit must be pro- grammed high. when the range bit is high, the chrominance pix els (both cr and cb) are saturated to the range 2 to 253, and the luminance range is limited to the range 16 to 253. in spi mode 2, the follo wing v alues are inserted as control codes to indicate video e v ents (see t able 2-2 ): the chroma v alues of 255 and 254, and the luminance v alues of 0 to 15. a chroma v alue of 255 indicates that the associated luma pix el is a control code; a pix el v alue of 255 indicates that the cbflag is high (i.e., the current pix el is a cb pix el). similarly , a pix el v alue of 254 indicates that the luma v alue is a control code, and that the cbflag is lo w (cr pix el). the ? rst pix el of a line is guaranteed to be a cb ? ag. ho we v er , due to code precedence relationships, the hreset code may be delayed by one pix el, so hreset can occur on a cr or a cb pix el. also, at the be ginning of a ne w ? eld, the relationship between vreset and hreset may be lost, typically with video from a vcr. as a result, vreset can occur during either a cb or a cr pix el. figure 2-10 demonstrates coded control for spi mode 2 (bytestream). t able 2-2 sho ws pix el data output ranges. independent of range, decimal 128 indicates zero color information for cr and cb . black is decimal 16 when range = 0 and code 0 when range = 1. figures 2-11 and 2-12 illustrate videotiming for spi modes 1 and 2. t able 2-2. description of the control codes in the pixel stream luma value chroma value video event description 0x00 0xff 0xfe this is an invalid pixel; last valid pixel was a cb pixel. this is an invalid pixel; last valid pixel was a cr pixel. 0x01 0xff 0xfe cb pixel; last pixel was the last active pixel of the line. cr pixel; last pixel was the last active pixel of the line. 0x02 0xff 0xfe cb pixel; next pixel is the ? rst active pixel of the line. cr pixel; next pixel is the ? rst active pixel of the line.
59 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa 0x03 0xff 0xfe cb pixel; hreset of a vertical active line. cr pixel; hreset of a vertical active line. 0x04 0xff 0xfe cb pixel; hreset of a vertical blank line. cr pixel; hreset of a vertical blank line. 0x05 0xff 0xfe cb pixel; vreset followed by an even ? eld. cr pixel; vreset followed by an even ? eld. 0x06 0xff 0xfe cb pixel; vreset followed by an odd ? eld. cr pixel; vreset followed by an odd ? eld. t able 2-2. description of the control codes in the pixel stream luma value chroma value video event description figure 2-10. data output in spi mode 2 (bytestream) clkx2 vd(15:8) 0xff 0x04 0xff 0x03 ? ? ? hreset , beginning of hor iz ontal line dur ing activ e video cb pix el cb pix el hreset : beginning of hor iz ontal line dur ing v er tical b lanking ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xff 0x02 cb y cr y first activ e pix el of the line in v alid pix el dur ing activ e video last v alid pix el w as a cb pix el cb y 0xff 0x00 cr y cb y 0xfe 0x01 xx xx last pix el of the line (cb pix el) last pix el code (cr pix el) cr pix el vreset : an odd ? eld f ollo ws xx xx 0xfe 0x06 xx xx activ e pix el of the line ne xt pix el is ? rst
60 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa figure 2-11. video t iming in spi modes 1 and 2 notes: (1). hreset precedes vreset by two clock cycles at the beginning of fields 1, 3, 5, and 7 to facilitate external field generation. 2. active pin may be programmed to be composite active or horizontal active. 3. active, hreset , vreset and field are shown with their default polarity. the polarity is programmable via the vpole register. 4. field transitions with the end of horizontal active video, defined by hdelay and hactive. 2C6 scan lines hreset vreset a ctive field vdela y/2 scan lines beginning of fields 1, 3, 5, 7 (1) 2C6 scan lines hreset vreset a ctive field vdela y/2 scan lines beginning of fields 2, 4, 6, 8
61 2.0 electrical interfaces 2.2 output interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.2.5 ccir601 compliance when the range bit is set to zero, the output le v els are fully compliant with the ccir601 recommendation. ccir601 speci? es that nominal video will ha v e y v alues ranging from 16 to 235, and that cr and cb v alues will range from 16 to 240. excursions outside this range are allo wed to handle non standard video. the only mandatory requirement is that 0 and 255 be reserv ed for timing information. figure 2-12. horizontal t iming signals in the spi modes hdela y cloc k cycles at fdesired ha ctive cloc k cycles 64 cloc k cycles at fclkx1 hreset a ctive at fdesired t able 2-3. data output ranges range = 0 range = 1 y 16 > 235 0 > 255 cr 2 > 253 2 > 253 cb 2 > 253 2 > 253
62 2.0 electrical interfaces 2.3 i 2 c interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.3 i 2 c interface the inter -inte grated circuit b us is a tw o-wire serial interf ace. serial clock (scl) and data lines (sd a) are used to transfer data between the b us master and the sla v e de vice. the bt829b can transfer data at a maximum rate of 100 kbps. the bt829b operates as a sla v e de vice. 2.3.1 starting and stopping the relationship between scl and sd a is decoded to pro vide both a start and stop condition on the b us. t o initiate a transfer on the i 2 c b us, the master must transmit a start pulse to the sla v e de vice. this is accomplished by taking the sd a line lo w while the scl line is held high. the master should only generate a start pulse at the be ginning of the c ycle, or after the transfer of a data byte to or from the sla v e. t o terminate a transfer , the master must tak e the sd a line high while the scl line is held high. the master may issue a stop pulse at an y time during an i 2 c c ycle. since the i 2 c b us will interpret an y transition on the sd a line during the high phase of the scl line as a start or stop pulse, care must be tak en to ensure that data is stable during the high phase of the clock. figure 2-13 illus- trates the relationship between scl and sd a. figure 2-13. the relationship between scl and sda star t stop sd a scl
63 2.0 electrical interfaces 2.3 i 2 c interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.3.2 addressing the bt829b an i 2 c sla v e address consists of tw o parts: a 7-bit base address and a single bit r/ w command. the r/ w bit is appended to the base address to form the transmit- ted i 2 c address, as sho wn in figure 2-14 and t able 2-4 . 2.3.3 reading and writing after transmitting a start pulse to initiate a c ycle, the master must address the bt829b. t o do this, the master must transmit one of the four v alid bt829b addresses, with the most signi? cant bit (msb) transmitted ? rst. after transmit- ting the address, the master must release the sd a line during the lo w phase of the scl and w ait for an ackno wledgment. if the transmitted address matches the selected bt829b address, the bt829b will respond by dri ving the sd a line lo w , generating an ackno wledge to the master . the master samples the sd a line at the rising edge of the scl line, and proceeds with the c ycle. if no de vice responds, including the bt829b, the master transmits a stop pulse and ends the c ycle. if the sla v e address r/ w bit w as lo w (indicating a write) the master will trans- mit an 8-bit byte to the bt829b, with the msb transmitted ? rst. the bt829b ackno wledges the transfer and loads the data into its internal address re gister . the master then issues a stop command, a start command, or transfers another 8-bit byte, msb ? rst. the internal address re gister points to the 8-bit byte, which is then loaded into the re gister . the bt829b ackno wledges the transfer and incre- ments the address re gister in preparation for the ne xt transfer . as before, the mas- ter may issue a stop command, a start command, or transfer another 8 bits which is loaded into the ne xt re gister location. if the sla v e address r/ w bit w as high (indicating a read), the bt829b transfers the contents of the re gister . its internal address re gister points to the contents, msb ? rst. the master ackno wledges receipt of the data and pulls the sd a line lo w . as with the write c ycle, the address re gister is auto-incremented in prepara- tion for the ne xt read. figure 2-14. i 2 c slave address con? guration a6 a5 a4 a3 a2 a1 a0 r/ w base address r/w bit t able 2-4. bt829b address matrix i2ccs pin bt829b base r/ w bit action 0 1000100 0 write 1000100 1 read 1 1000101 0 write 1000101 1 read
64 2.0 electrical interfaces 2.3 i 2 c interface bt829b/827b v ideostr eam ii decoders d829bdsa t o stop a read transfer , the host must not ackno wledge the last read c ycle. the bt829b then releases the data b us in preparation for a stop command. if an ackno wledgment is recei v ed, the bt829b proceeds to transfer the ne xt re gister . when the master generates a read from the bt829b, the bt829b starts its transfer from whate v er location is currently loaded into the address re gister . since the address re gister might not contain the address of the desired re gister , the mas- ter generally e x ecutes a write c ycle, setting the address re gister to the desired location. after recei ving an ackno wledgment for the transfer of the data into the address re gister , the master initiates a read of the bt829b by starting a ne w i 2 c c ycle with an appropriate read address. the bt829b then transfers the contents of the desired re gister . f or e xample, to read re gister 0x0a, brightness control, the master starts a write c ycle with an i 2 c address of 0x88 or 0x8a. after recei ving an ackno wledg- ment from the bt829b, the master transmits the desired address, 0x0a. after recei ving an ackno wledgment, the master then starts a read c ycle with an i 2 c sla v e address of 0x89 or 0x8b. the bt829b ackno wledges and transfers the con- tents of re gister 0x0a. there is no need to issue a stop command after the write c ycle. the bt829b detects the repeated start command and starts a ne w i 2 c c ycle. this process is illustrated in t able 2-5 and figure 2-15 . f or detailed information on the i 2 c b us, refer to the i 2 c-bus refer ence guide, reprinted by rockwell. t able 2-5. example i 2 c data t ransactions master data flow bt829b comment write to bt829b i 2 c start > master sends bt829b chip address, i.e., 0x88 or 0x8a. ack bt829b generates ack on successful receipt of chip address. subaddress > master sends subaddress to bt829b. ack bt829b generates ack on successful receipt of subaddress. data(0) > master sends ? rst data byte to bt829b. ack(0) bt829b generates ack on successful receipt of ? rst data byte. . . . > > > . . . data(n) > master sends nth data byte to bt829b. ack(n) bt829b generates ack on successful receipt of nth data byte. i 2 c stop master generates stop to end transfer .
65 2.0 electrical interfaces 2.3 i 2 c interface bt829b/827b v ideostr eam ii decoders d829bdsa read from bt829b i 2 c start > master sends bt829b chip address, i.e., 0x89 or 0x8b. ack bt829b generates ack on successful receipt of chip address. < data(0) bt829b sends ? rst data byte to master . ack(0) master generates ack on successful receipt of ? rst data byte. . . . < < < . . . < data(n-1) bt829b sends (n-1)th data byte to master . ack(n-1) master generates ack on successful receipt of (n-1)th data byte. < data(n) bt829b sends nth data byte to master . no ack master does not acknowledge nth data byte. i 2 c stop master generates stop to end transfer . t able 2-5. example i 2 c data t ransactions master data flow bt829b comment where: i 2 c star t = i 2 c start condition and bt829b chip address (including the r/ w bit). subaddress = the 8-bit subaddress of the bt829b register, msb first. data(n) = the data to be transferred to/from the addressed register. i 2 c stop = i 2 c stop condition.
66 2.0 electrical interfaces 2.3 i 2 c interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.3.4 software reset the contents of the control re gisters may be reset to their def ault v alues by issu- ing a softw are reset. a softw are reset can be accomplished by writing an y v alue to subaddress 0x1f . a read of this location returns an unde? ned v alue. figure 2-15. i 2 c protocol diagram chip addr d a t a s a sr a a chip addr sub-addr s a a a a p chip addr sub-addr s a a chip addr a d a t a d a t a d a t a data read data wr ite wr ite f ollo w ed b y read 0x89 or 0x8b repeated 8 bits f rom master to bt829b f rom bt829b to master s = start sr = repeated start p = stop a = acknowledge na = non acknowledge 0x88 or 0x8a 0x88 or 0x8a na p d a t a d a t a a a a a d a t a data na p d a t a a register p ointed to b y subaddress star t
67 2.0 electrical interfaces 2.4 jt ag interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.4 jt ag interface 2.4.1 need for functional v eri? cation as the comple xity of imaging chips increases, the need to easily access indi vidual chips for functional v eri? cation is vital. the bt829b incorporates special circuitry which mak es it accessible in full compliance with joint t est action group (jt a g) standards. conforming to ieee p1149.1 standard t est access port and boundary scan architecture, the bt829b contains dedicated pins used only for testability purposes. 2.4.2 jt ag approach to t estability jt a g s approach to testability uses boundary scan cells that are placed at each digital pin and digital interf ace. (a digital interf ace is de? ned as the boundary between an analog block and a digital block within the bt829b). all cells are interconnected into a boundary scan re gister that applies or captures test data to v erify functionality of the inte grated circuit. jt a g is particularly useful for board testers using functional testing methods. jt a g consists of ? v e dedicated pins comprising the t est access port (t ap). these pins are t est mode select (tms), t est clock (tck), t est data input (tdi), t est data out (tdo), and t est reset ( trst ). the trst pin resets the jt a g controller when pulled lo w at an y time. v eri? cation of the inte grated circuit and its connection to other modules on the printed circuit board is achie v ed through these ? v e t ap pins. w ith boundary scan cells at each digital interf ace and pin, the bt829b is capable of applying and capturing the respecti v e logic le v- els. because all of the digital pins are interconnected as a long shift re gister , the t ap logic has access to the necessary pins. this ensures v eri? cation of pin func- tionality . the t ap controller can shift in an y number of test v ectors through the tdi input and can apply them to the internal circuitry . the output result is scanned on the tdo pin and is e xternally check ed. while isolating the bt829b from other components on the board, the user has easy access to all bt829b digi- tal pins and digital interf aces through the t ap . the user can then perform com- plete functionality tests without using e xpensi v e bed-of-nails testers.
68 2.0 electrical interfaces 2.4 jt ag interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.4.3 optional device id register the bt829b has the optional de vice identi? cation re gister de? ned by the jt a g speci? cation. this re gister contains information concerning the re vision, actual part number , and manuf acturer s identi? cation code that is speci? c to rockwell. the t ap controller can access the re gister via an optional jt a g instruction, as sho wn in t able 2-6 . 2.4.4 v eri? cation with the t ap controller the t ap controller enables you to perform a v ariety of v eri? cation procedures. using a set of four instructions, the bt829b can v erify board connecti vity at all digital interf aces and pins. the instructions can be accessed using a state machine that is standard to all jt a g controllers. the y are sample/preload, extest, id code, and bypass (see figure 2-16 ). refer to the ieee p1149.1 speci? cation for details concerning the instruction re gister and jt a g state machine. rockwell has created a bsdl with the a t&t bsd editor . if you plan to implement jt a g testing, you may obtain a disk with an ascii v ersion of the complete bsdl ? le by contacting your local rockwell sales of ? ce. t able 2-6. device identi? cation register version part number manufacturer id x x x x 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1 0 0829, 0x033d 0x0d6 4 bits 16 bits 11 bits note: the part number remains the same for both parts: bt829b and BT827B. figure 2-16. instruction register tdi tdo extest 0 0 sample/preload 0 0 id code 0 1 bypass 1 1
69 2.0 electrical interfaces 2.4 jt ag interface bt829b/827b v ideostr eam ii decoders d829bdsa 2.4.5 example bsdl listing attribute boundary_register of bt829b : entity is 0 (bc_1, *, control, 1), & 1 (bc_1, *, internal, 1), & 2 (bc_1, *, control, 1), & 3 (bc_1, *, internal, x), & 4 (bc_1, *, internal, x), & 5 (bc_1, *, internal, x), & 6 (bc_1, *, internal, x), & 7 (bc_1, *, internal, x), & 8 (bc_1, *, internal, x), & 9 (bc_1, *, internal, x), & 10 (bc_1, *, internal, x), & 11 (bc_1, *, internal, x), & 12 (bc_1, *, internal, x), & 13 (bc_1, *, internal, 0), & 14 (bc_1, *, internal, 0), & 15 (bc_1, *, internal, 0), & 16 (bc_1, *, internal, 0), & 17 (bc_1, *, internal, 0), & 18 (bc_1, *, internal, 0), & 19 (bc_1, *, internal, 0), & 20 (bc_1, *, internal, 0), & 21 (bc_1, *, internal, 0), & 22 (bc_1, *, internal, 0), & 23 (bc_1, *, internal, 0), & 24 (bc_1, *, internal, 0), & 25 (bc_1, *, internal, 0), & 26 (bc_1, *, internal, 0), & 27 (bc_1, *, internal, 0), & 28 (bc_1, *, control, 0), & 29 (bc_1, field, output3, x, 28, 0, z), & 30 (bc_1, nvreset, output3, x, 28, 0, z), & 31 (bc_1, xtfmt, input, x), & 32 (bc_1, nhreset, output3, x, 28, 0, z), & 33 (bc_1, active, output3, x, 28, 0, z), & 34 (bc_1, dvalid, output3, x, 28, 0, z), & 35 (bc_1, vactive, output3, x, 28, 0, z), & 36 (bc_1, tst, output2, 0, 36, 0, weak1), & 37 (bc_1, *, internal, x), &
70 2.0 electrical interfaces 2.4 jt ag interface bt829b/827b v ideostr eam ii decoders d829bdsa 38 (bc_1, cbflag, output3, x, 28, 0, z), & 39 (bc_3, nvsen, input, x), & 40 (bc_1, pwrdn, input, x), & 41 (bc_1, qclk, output3, x, 28, 0, z), & 42 (bc_1, clkx1, output3, x, 28, 0, z), & 43 (bc_1, noe, input, 1), & 44 (bc_1, clkx2, output3, x, 28, 0, z), & 45 (bc_1, vdb(13), output3, x, 28, 0, z), & 46 (bc_1, vdb(14), output3, x, 28, 0, z), & 47 (bc_1, vdb(15), output3, x, 28, 0, z), & 48 (bc_1, vdb(8), output3, x, 28, 0, z), & 49 (bc_1, vdb(9), output3, x, 28, 0, z), & 50 (bc_1, vdb(10), output3, x, 28, 0, z), & 51 (bc_1, vdb(11), output3, x, 28, 0, z), & 52 (bc_1, vdb(12), output3, x, 28, 0, z), & 53 (bc_1, *, internal, x), & 54 (bc_1, xt0i, input, x), & 55 (bc_1, i2ccs, input, x), & 56 (bc_1, nrst, input, x), & 57 (bc_1, *, internal, x), & 58 (bc_1, xt1i, input, x), & 59 (bc_1, sda, output2, 0, 59, 1, pull1), & 60 (bc_1, sda, input, x), & 61 (bc_1, scl, input, x), & 62 (bc_1, vda(3), output3, x, 0, 1, z), & 63 (bc_1, vda(3), input, x), & 64 (bc_1, vda(4), output3, x, 2, 1, z), & 65 (bc_1, vda(4), input, x), & 66 (bc_1, vda(5), output3, x, 2, 1, z), & 67 (bc_1, vda(5), input, x), & 68 (bc_1, vda(6), output3, x, 2, 1, z), & 69 (bc_1, vda(6), input, x), & 70 (bc_1, vda(7), output3, x, 2, 1, z), & 71 (bc_1, vda(7), input, x), & 72 (bc_1, vda(0), output3, x, 0, 1, z), & 73 (bc_1, vda(0), input, x), & 74 (bc_1, vda(1), output3, x, 0, 1, z), & 75 (bc_1, vda(1), input, x), & 76 (bc_1, vda(2), output3, x, 0, 1, z), & 77 (bc_1, vda(2), input, x), &
71 2.0 electrical interfaces 2.4 jt ag interface bt829b/827b v ideostr eam ii decoders d829bdsa 78 (bc_1, twren, input, x), & 79 (bc_0, *, internal, 0), & 80 (bc_0, *, internal, 0); end bt829b;
72 2.0 electrical interfaces 2.4 jt ag interface bt829b/827b v ideostr eam ii decoders d829bdsa
73 d829bdsa 3.0 pc board layout considerations the layout should be optimized for lo west noise on the bt829b po wer and ground lines. optimization is achie v ed by shielding the digital inputs and outputs and by pro viding good decoupling. the lead length between groups of po wer and ground pins should be minimized to reduce inducti v e ringing. 3.1 ground planes the ground plane area should encompass all bt829b ground pins, v oltage refer - ence circuitry , po wer supply bypass circuitry for the bt829b, analog input traces, an y input ampli? ers, and all the digital signal traces leading to the bt829b. the bt829b has digital grounds (gnd) and analog grounds (a gnd and vneg). the layout for the ground plane should be set up so the tw o planes are at the same electrical potential, b ut the y should be isolated from each other in the areas surrounding the chip. the return path for the current should be through the digital plane. see figure 3-1 for an e xample of ground plane layout. figure 3-1. example of ground plane layout bt829b 1 50 analog ground digital ground ground retur n (i.e ., pci bus connection) circuit board edge
74 3.0 pc board layout considerations 3.1 ground planes bt829b/827b v ideostr eam ii decoders d829bdsa 3.1.1 power planes the po wer plane area should encompass all bt829b po wer pins, v oltage reference circuitry , po wer supply bypass circuitry for the bt829b, analog input traces, an y input ampli? ers, and all the digital signal traces leading to the bt829b. the bt829b has digital po wer (vdd) and analog po wer (v aa and vpos). the layout for the po wer plane should be set up so the tw o planes are at the same electrical potential, b ut the y should be isolated from each other in the areas sur - rounding the chip. the return path for the current should be through the digital plane. this is the same layout as the ground plane ( figure 3-1 ). when using a re g- ulator , circuitry must be included to ensure proper po wer sequencing. figure 3-2 illustrates this circuitry layout. figure 3-2. optional regulator circuitr y in system p o w er v aa, vdd out ground gnd suggested p ar t numbers: regulator t e xas instr uments m a78 mo5m (+5 v) system p o w er (+5 v) (+12 v) diodes m ust handle of the bt829b and the per ipher al circuitr y . the current requirements
75 3.0 pc board layout considerations 3.1 ground planes bt829b/827b v ideostr eam ii decoders d829bdsa 3.1.2 supply decoupling the bypass capacitors should be installed with the shortest leads possible (consis- tent with reliable operation) to reduce the lead inductance. these capacitors should be placed as close as possible to the de vice. each group of v aa and vdd pins should ha v e a 0.1 m f ceramic bypass capacitor to ground, located as close as possible to the de vice. additionally , 10 m f capacitors should be connected between the analog po wer and ground planes, as well as between the digital po wer and ground planes. these capacitors are at the same electrical potential, b ut pro vide additional decoupling by being ph ysically close to the bt829b po wer and ground planes. f or additional information about po wer supply decoupling, see figures 3-3 and 3-4 . figure 3-3. t ypical power and ground connection diagram and parts list for 5 v i/o mode +5 v (vcc) ground + + c1 c3 c4 vdd , vddo v aa, vpos gnd bt829b a gnd , vneg + analog area + c2 location description vendor part number c1, c2 (1) 0.1 m f ceramic capacitor erie rpe112z5u104m50v c3, c4 (2) 10 m f tantalum capacitor mallor y csr13g106km notes: (1). a 0.1 m f capacitor should be connected between each group of power pins and ground. they should be connected as close to the device as possible (ceramic chip capacitors are preferred). (2). the 10 m f capacitors should be connected between the analog supply and the analog ground, as well as the digital supply and the digital ground. these should be connected as close to the bt829b as possible. 3. vendor numbers are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt829b.
76 3.0 pc board layout considerations 3.1 ground planes bt829b/827b v ideostr eam ii decoders d829bdsa figure 3-4. t ypical power and ground connection diagram and parts list for 3.3 v i/o mode +5 v (vcc) ground + + c1 c3 c4 vdd v aa, vpos gnd bt829b a gnd , vneg + analog area + c2 vddo c5 +3.3 v location description vendor part number c1, c2 (1) , c5 0.1 m f ceramic capacitor erie rpe112z5u104m50v c3, c4 (2) 10 m f tantalum capacitor mallor y csr13g106km notes: (1). a 0.1 m f capacitor should be connected between each group of power pins and ground. they should be connected as close to the device as possible (ceramic chip capacitors are preferred). (2). the 10 m f capacitors should be connected between the analog supply and the analog ground, as well as the digital supply and the digital ground. these should be connected as close to the bt829b as possible. 3. vendor numbers are listed only as a guide. substitution of devices with similar characteristics will not affect the performance of the bt829b.
77 3.0 pc board layout considerations 3.1 ground planes bt829b/827b v ideostr eam ii decoders d829bdsa 3.1.3 digital signal interconnect the digital signals of the bt829b should be isolated as much as possible from the analog signals and other analog circuitry . also, the digital signals should not o v er - lay the analog po wer plane. an y termination resistors for the digital signals should be connected to the re gular pcb po wer and ground planes. 3.1.4 analog signal interconnect t o minimize crosstalk, long lengths of closely spaced parallel video signals should be a v oided. ideally , a ground line should e xist between the video signal traces dri ving the yin and cin inputs. t o minimize noise coupling, high-speed ttl signals should not be routed close to the analog signals. 3.1.5 latch-up a voidance latch-up is a f ailure mechanism inherent to an y cmos de vice. it is triggered by static or impulse v oltages on an y signal input pin when the v oltage on the po wer pins e xceeds 0.5 v , or when it f alls belo w the gnd pins by more than 0.5 v . latch-up can also occur if the v oltage on an y po wer pin e xceeds the v oltage on an y other po wer pin by more than 0.5 v . in some cases, de vices with mix ed signal interf aces, such as the bt829b, can appear more sensiti v e to latch-up. mix ed signal de vices tend to interact with peripheral de vices, such as video monitors or cameras that are referenced to dif- ferent ground potentials. v oltages applied to the de vice prior to the time that its po wer system is stable can create conditions that are amenable to the onset of latch-up. t o maintain a rob ust design with the bt829b, you should tak e the follo wing precautions: ? apply po wer to the de vice before or at the same time that po wer is applied to the interf ace circuitry . ? do not apply v oltages belo w gndC0.5 v or higher than v aa+0.5 v to an y pin on the de vice. do not use ne g ati v e supply op-amps or an y other ne g a- ti v e v oltage interf ace circuitry . all logic inputs should be held lo w until po wer to the de vice has settled to the speci? ed tolerance. ? connect all vdd, v aa, and vpos pins together through a lo w impedance plane. ? connect all gnd, a gnd, and vneg pins together through a lo w impedance plane.
78 3.0 pc board layout considerations 3.1 ground planes bt829b/827b v ideostr eam ii decoders d829bdsa
79 d829bdsa 4.0 control register definitions this section describes the function of the v arious control re gisters in detail. t able 4-1 summarizes the re gister functions. t able 4-1. register map (1 of 2) register name mnemonic register address 640 x 480 square pixel ntsc (default) 768 x 576 square pixel pal/secam 720 x 480 ccir ntsc 720 x 576 ccir pal/secam 320 x 240 2:1 ntsc (square pixel, cif) 320 x 288 2:1 pal/secam (square pixel, cif) device status st a tus 0x00 0x00 0x00 0x00 0x00 0x00 0x00 input format iform 0x01 0x58 0x78 0x58 0x78 0x58 0x78 t emporal decimation tdec 0x02 0x00 0x00 0x00 0x00 0x00 0x00 msb cropping crop 0x03 0x12 0x23 0x12 0x23 0x11 0x21 v ertical delay , lower byte vdela y_lo 0x04 0x16 0x16 0x16 0x16 0x16 0x16 v ertical active, lower byte v active_lo 0x05 0xe0 0x40 0xe0 0x40 0xe0 0x40 horizontal delay , lower byte hdela y_lo 0x06 0x78 0x9a 0x80 0x90 0x40 0x48 horizontal active, lower byte hactive_lo 0x07 0x80 0x00 0xd0 0xd0 0x40 0x80 horizontal scaling, upper byte hscale_hi 0x08 0x02 0x03 0x00 0x05 0x11 0x1a horizontal scaling, lower byte hscale_lo 0x09 0xac 0x3c 0xf8 0x04 0xf0 0x09 brightness control bright 0x0a 0x00 0x00 0x00 0x00 0x00 0x00 miscellaneous control control 0x0b 0x20 0x20 (1) 0x20 0x20 (1) 0x20 0x20 luma gain, lower byte (contrast) contrast_lo 0x0c 0xd8 0xd8 0xd8 0xd8 0xd8 0xd8 chroma (u) gain, lower byte (saturation) sa t_u_lo 0x0d 0xfe 0xfe 0xfe 0xfe 0xfe 0xfe chroma (v) gain, upper byte (saturation) sa t_v_lo 0x0e 0xb4 0xb4 0xb4 0xb4 0xb4 0xb4
80 4.0 control register de? nitions bt829b v ideostr eam ii decoders d829bdsa hue control hue 0x0f 0x00 0x00 0x00 0x00 0x00 0x00 sc loop control scloop 0x10 0x00 0x00 (1) 0x00 0x00 (1) 0x00 0x00 white crush up count wc_up 0x11 0xcf 0xcf 0xcf 0xcf 0xcf 0xcf output format oform 0x12 0x06 0x06 0x06 0x06 0x06 0x06 v ertical scaling, upper byte vscale_hi 0x13 0x60 0x60 0x60 0x60 0x40 (1) 0x40 (1) v ertical scaling, lower byte vscale_lo 0x14 0x00 0x00 0x00 0x00 0x00 0x00 t est control test 0x15 0x01 0x01 0x01 0x01 0x01 0x01 video t iming polarity register vpole 0x16 0x00 0x00 0x00 0x00 0x00 0x00 id code idcode 0x17 0x70 0x70 0x70 0x70 0x70 0x70 agc delay adela y 0x18 0x68 0x7f 0x68 0x7f 0x68 0x7f burst gate delay bdela y 0x19 0x5d 0x72 (1) 0x5d 0x72 (1) 0x5d 0x72 adc inter face adc 0x1a 0x82 0x82 0x82 0x82 0x82 0x82 video t iming control vtc 0x1b 0x00 0x00 0x00 0x00 0x00 0x00 extended data ser - vices/closed caption status cc_st a tus 0x1c 0x00 0x00 0x00 0x00 0x00 0x00 extended data ser - vices/closed caption data cc_da t a 0x1d 0x00 0x00 0x00 0x00 0x00 0x00 white crush down count wc_dn 0x1e 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f software reset sreset 0x1f programmable i/o p_io 0x3f secam video register diff erences miscellaneous control control 0x00 0x00 sc loop control scloop 0x10 0x10 burst gate delay bdela y 0xa0 0xa0 notes: (1). secam video register differences to pal video. (2). when using one ? eld, no additional vertical scaling is necessar y for cif resolutions. the int bit in register 0xb(vscale_hi) should be set to a logical 0 when scaling from only one ? eld. t able 4-1. register map (2 of 2) register name mnemonic register address 640 x 480 square pixel ntsc (default) 768 x 576 square pixel pal/secam 720 x 480 ccir ntsc 720 x 576 ccir pal/secam 320 x 240 2:1 ntsc (square pixel, cif) 320 x 288 2:1 pal/secam (square pixel, cif)
81 4.0 control register de? nitions 0x00 device status register (st a tus) bt829b v ideostr eam ii decoders d829bdsa 0x00 device status register (st a tus) \the mpu can read or write to this re gister at an y time. upon reset, it is initialized to 0x00. cof is the lsb. by writing to the re gister , the cof and lof status bits hold their v alues until reset to their def ault v alues. the other six bits do not hold their v alues, b ut continually output the status. an asterisk indicates the def ault option. pres v ideo present statusv ideo is determined to be not present when an input sync is not detected in 31 consecuti v e line periods. 0* = v ideo not present 1 = v ideo present hloc de vice in h-lockif hsync is found within 1 clock c ycle of the e xpected position of hsync for 32 consecuti v e lines, this bit is set to a logical 1. once set, if hsync is not found within 1 clock c ycle of the e xpected position of hsync for 32 consecuti v e lines, this bit is set to a logical 0. mpu writes to this bit are ignored. this bit indicates the stability of the incoming video. although it is an indicator of horizontal locking, some video sources charac- teristically v ary from line-to-line by more than one clock c ycle. this causes the bit to ne v er be set. consumer vcrs are e xamples of sources that tend to ne v er set this bit. 0* = de vice not in h-lock 1 = de vice in h-lock field field statusthis bit re? ects whether an odd or e v en ? eld is being decoded. the field bit is determined by the relationship between hreset and vreset . 0* = odd ? eld 1 = ev en ? eld numl number of linesthis bit identi? es the number of lines found in the video stream. this bit is used to determine the type of video input to the bt829a. thirty tw o consecuti v e ? elds with the same number of lines is required before this status bit will change. 0* = 525-line format (ntsc/p al-m) 1 = 625-line format (p al/secam) csel crystal selectthis bit identi? es which crystal port is selected. when automatic format detection is enabled, this bit will be the same as numl. 0* = xt al0 input selected 1 = xt al1 input selected ccv alid v alid closed caption datathis bit indicates that v alid closed caption or extended data ser - vices (eds) sample pairs ha v e been stored in the closed caption data re gisters. this bit indi- cates that the closed caption data fifo is half full. it is reset after being written to or when a chip reset occurs. 7 6 5 4 3 2 1 0 pres hloc field numl csel ccv alid lof cof 0 0 0 0 0 0 0 0
82 4.0 control register de? nitions 0x01input format register (iform) bt829b v ideostr eam ii decoders d829bdsa lof luma adc ov er? o won po wer -up, this bit is set to 0. if an adc o v er? o w occurs, the bit is set to a logical 1. it is reset after being written to, or when a chip reset occurs. when the adc is in po wer -do wn mode (y_sleep = 1) the state of this bit is not v alid and should be ignored. when the luma a/d is in sleep mode, lof is set to 1. cof chroma adc ov er? o won po wer -up, this bit is set to 0. if an adc o v er? o w occurs, the bit is set to a logical 1. it is reset after being written to, or when a chip reset occurs. when the adc is in po wer -do wn mode (c_sleep = 1), the state of this bit is not v alid and should be ignored. when the chroma a/d is in sleep mode, cof is set to 1. 0x01input format register (iform) the mpu may read or write to this control re gister at an y time. upon reset, it is initialized to 0x58. forma t(0) is the lsb. an asterisk indicates the def ault option. hactive when using the bt829a with a pack ed memory architecture, for e xample, with ? eld memo- ries, this bit should be programmed with a logical 1. when implementing a vram based architecture, this bit should be programmed with a logical 0. 0* = reset ha ctive with hreset 1 = extend ha ctive be yond hreset muxsel this bit is used for softw are control of video input selection. the bt829a can select between four composite video sources, or three composite and one s-v ideo source. 00 = select mux3 input to muxout 01 = select mux2 input to muxout 10* = select mux0 input to muxout 11 = select mux1 input to muxout xtsel if automatic format detection is required, logical 11 must be loaded. logical 01 and 10 are used if softw are format selection is desired. 00 = reserv ed 01 = select xt0 input (only xt0 present) 10 = select xt1 input (both xts present) 11* = auto xt select enabled (both xts present) forma t automatic format detection may be enabled or disabled. the numl bit is used to determine the input format when automatic format detection is enabled. 000* = auto format detect enabled 001 = ntsc (m) input format 010 = ntsc with no pedestal format 011 = p al (b, d, g, h, i) input format 100 = p al (m) input format 101 = p al (n) input format 110 = secam input format 111 = p al (n combination) input format 7 6 5 4 3 2 1 0 hactive muxsel xtsel forma t 0 1 0 1 1 0 0 0
83 4.0 control register de? nitions 0x02t emporal decimation register (tdec) bt829b v ideostr eam ii decoders d829bdsa 0x02t emporal decimation register (tdec) the mpu can read or write to this control re gister at an y time. upon reset, it is initialized to 0x00. dec_ra t(0) is the lsb. this re gister enables temporal decimation by discarding a ? nite number of ? elds or frames from the incoming video. an asterisk indicates the def ault option. dec_field this bit de? nes whether decimation occurs according to ? elds or frames. 0* = decimate frames 1 = decimate ? elds fldalign this bit aligns the start of decimation with an e v en or odd ? eld. 0* = start decimation on the odd ? eld (an odd ? eld is the ? rst ? eld dropped). 1 = start decimation on the e v en ? eld (an e v en ? eld is the ? rst ? eld dropped). dec_ra t dec_ra t is the number of ? elds or frames dropped out of 60 ntsc or 50 p al/secam ? elds or frames. 0x00 v alue disables decimation (all video frames and ? elds are output). note: use caution when changing the programming in the tdec re gister . 0x00 must be loaded before the decimation v alue. this ensures that decimation does not start on the wrong ? eld or frame. the re gister should not be loaded with dec_ra t greater than 60 (0x3c) for ntsc, or greater than 50 (0x34) for p al/secam. xx00 0000Cxx11 1111 = number of ? elds/frames dropped. 0x03msb cropping register (crop) the mpu can read or write to this control re gister at an y time. upon reset, it is initialized to 0x12. ha ctive_msb(0) is the lsb. see the v a ctive, vdela y , ha ctive, and hdela y re gisters for descrip- tions on the operation of this re gister . vdela y_msb 00xx xxxxC11xx xxxx = the most signi? cant tw o bits of v ertical delay re gister . v active_msb xx00 xxxxCxx11 xxxx = the most signi? cant tw o bits of v ertical acti v e re gister . hdela y_msb xxxx 00xxCxxxx 11xx = the most signi? cant tw o bits of horizontal delay re gister . hactive_msb xxxx xx00Cxxxx xx11 = the most signi? cant tw o bits of horizontal acti v e re gister . 7 6 5 4 3 2 1 0 dec_field fldalign dec_ra t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 vdela y_msb v active_msb hdela y_msb hactive_msb 0 0 0 1 0 0 1 0
84 4.0 control register de? nitions 0x04v ertical delay register , lower byte (vdela y_lo) bt829b v ideostr eam ii decoders d829bdsa 0x04v ertical delay register , lower byte (vdela y_lo) the mpu can read or write to this control re gister at an y time. upon reset, it is initialized to 0x16. the lsb (lsb) is vdela y_lo(0). this 8-bit re gister is the lo wer byte of the 10-bit vdela y re gister . the cr op re g- ister contains the tw o msbs of vdela y . vdela y de? nes the number of half lines between the trailing edge of vreset and the start of acti v e video. vdela y_lo 0x01C0xff = the lsbyte of the v ertical delay re gister . 0x05v ertical active register , lower byte (v active_lo) the mpu can read or write to this control re gister at an y time. upon reset, it is initialized to 0xe0. the lsb is v a ctive_lo(0). this 8-bit re gister is the lo wer byte of the 10-bit v a ctive re gister . the cr op re gister con- tains the tw o msbs of v a ctive. v a ctive de? nes the number of lines used in the v ertical scaling process. the actual number of lines output by the bt829a is scaling_ra tio * v a ctive. v active_lo 0x00C0xff = the lsbyte of the v ertical acti v e re gister . 0x06horizontal delay register , lower byte (hdela y_lo) the mpu can read or write to this control re gister at an y time. upon reset, it is initialized to 0x78. hdela y_lo(0) is the lsb. this 8-bit re gister is the lo wer byte of the 10-bit hdela y re gister . the tw o msbs of hdela y are contained in the cr op re gister . hdela y de? nes the number of scaled pix els between the f alling edge of hreset and the start of acti v e video. hdela y_lo 0x01C0xff = the lsbyte of the horizontal delay re gister . ha ctive pix els are output by the chip starting at the f all of hreset . caution: hdela y must be programmed with an e v en number . 7 6 5 4 3 2 1 0 vdela y_lo 0 0 0 1 0 1 1 0 7 6 5 4 3 2 1 0 v active_lo 1 1 1 0 0 0 0 0 7 6 5 4 3 2 1 0 hdela y_lo 0 1 1 1 1 0 0 0
85 4.0 control register de? nitions 0x07horizontal active register , lower byte (hactive_lo) bt829b v ideostr eam ii decoders d829bdsa 0x07horizontal active register , lower byte (hactive_lo) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x80. ha ctive_lo(0) is the lsb. ha ctive de? nes the number of horizontal acti v e pix els-per -line output by the bt829a. hactive_lo 0x00C0xff = the lsbyte of the horizontal acti v e re gister . this 8-bit re gister is the lo wer byte of the 10-bit ha ctive re gister . the cr op re gisters contains the tw o msbs of ha ctive. 0x08horizontal scaling register , upper byte (hscale_hi) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x02. this 8-bit re gister is the upper byte of the 16-bit hscale re gister . hscale_hi 0x00C0xff = the most signi? cant byte of the horizontal scaling ratio. 0x09horizontal scaling register , lower byte (hscale_lo) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0xa c. this 8-bit re gister is the lo wer byte of the 16-bit hscale re gister . hscale_lo 0x00C0xff = the lsbyte of the horizontal scaling ratio. 7 6 5 4 3 2 1 0 hactive_lo 1 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 hscale_hi 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 0 hscale_lo 1 0 1 0 1 1 0 0
86 4.0 control register de? nitions 0x0abrightness control register (bright) bt829b v ideostr eam ii decoders d829bdsa 0x0abrightness control register (bright) the brightness control in v olv es the addition of a tw o s complement number to the luma channel. brightness can be adjusted in 255 steps, from C128 to +127. the resolution of brightness change is one lsb 0.39% with respect to the full luma range. an asterisk indicates the def ault option. bright 7 6 5 4 3 2 1 0 bright 0 0 0 0 0 0 0 0 hex value binary value brightness changed by number of lsbs percent of full scale 0x80 1000 0000 C128 C100% 0x81 1000 0001 C127 C99.22% . . . . . . 0xff 1111 1111 C01 C0.78% 0x00* 0000 0000* 00 0% 0x01 0000 0001 +01 +0.78% . . . . . . 0x7e 0111 1110 +126 +99.2% 0x7f 0111 1111 +127 +100%
87 4.0 control register de? nitions 0x0bmiscellaneous control register (control) bt829b v ideostr eam ii decoders d829bdsa 0x0bmiscellaneous control register (control) the mpu can read or write to this control re gister at an y time. upon reset, it is initialized to 0x20. sa t_v_msb is the lsb. an asterisk indicates the def ault option. lnotch this bit is used to include the luma notch ? lter . f or monochrome video, the notch should not be used. this will output full bandwidth luminance. 0* = enable the luma notch ? lter 1 = disable the luma notch ? lter comp when comp is set to logical 1, the luma notch is disabled. when comp is set to logical 0, the c adc is disabled. 0* = composite v ideo 1 = y/c component v ideo ldec the luma decimation ? lter is used to reduce the high-frequenc y component of the luma signal. this is useful when scaling to cif resolutions or lo wer . 0 = enable luma decimation using selectable h ? lter 1* = disable luma decimation cbsense this bit controls whether the ? rst pix el of a line is a cb pix el or a cr pix el. f or e xample, if cbsense is lo w and hdela y is an e v en number , the ? rst acti v e pix el output is a cb pix el. if hdela y is odd, cbsense may be programmed high to produce a cb pix el as the ? rst acti v e pix el output. 0* = normal cb, cr order 1 = in v ert cb, cr order reser ved this bit should only be written with a logical 0. con_msb the most signi? cant bit of the luma g ain (contrast) v alue. sa t_u_msb the most signi? cant bit of the chroma (u) g ain v alue. sa t_v_msb the most signi? cant bit of the chroma (v) g ain v alue. 7 6 5 4 3 2 1 0 lnotch comp ldec cbsense reser ved con_msb sa t_u_msb sa t_v_msb 0 0 1 0 0 0 0 0
88 4.0 control register de? nitions 0x0cluma gain register , lower byte (contrast_lo) bt829b v ideostr eam ii decoders d829bdsa 0x0cluma gain register , lower byte (contrast_lo) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0xd8. contrast_lo(0) is the lsb. the con_l_msb bit and the contrast_lo re gister concatenate to form the 9-bit contrast re gister . the v alue in this re gister is multiplied by the luminance v alue to pro vide contrast adjustment. contrast_lo the least signi? cant byte (lsbyte) of the luma g ain (contrast) v alue. 7 6 5 4 3 2 1 0 contrast_lo 1 1 0 1 1 0 0 0 decimal value hex value % of original signal 511 0x1ff 236.57% 510 0x1fe 236.13% . . . . . . 217 0x0d9 100.46% 216 0x0d8 100.00% . . . . . . 128 0x080 59.26% . . . . . . 1 0x001 0.46% 0 0x000 0.00%
89 4.0 control register de? nitions 0x0dchroma (u) gain register , lower byte (sa t_u_lo) bt829b v ideostr eam ii decoders d829bdsa 0x0dchroma (u) gain register , lower byte (sa t_u_lo) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0xfe. sa t_u_lo(0) is the lsb. sa t_u_msb in the contr ol re gister and sa t_u_lo concatenate to gi v e a 9-bit re gister (sa t_u). this re gister is used to add a g ain adjustment to the u component of the video signal. by adjusting the u and v color components of the video stream by the same amount, the saturation is adjusted. f or normal saturation adjustment, the g ain in both the color dif ference paths must be the same (i.e., the ratio between the v alue in the u g ain re gister and the v alue in the v g ain re gister should be k ept constant at the def ault po wer -up ratio). when changing the saturation, if the sa t_u_msb bit is altered, care must be tak en to ensure that the other bits in the contr ol re gister are not af fected. sa t_u_lo 7 6 5 4 3 2 1 0 sa t_u_lo 1 1 1 1 1 1 1 0 decimal value hex value % of original signal 511 0x1ff 201.18% 510 0x1fe 200.79% . . . . . . 255 0x0ff 100.39% 254 0x0fe 100.00% . . . . . . 128 0x080 50.39% . . . . . . 1 0x001 0.39% 0 0x000 0.00%
90 4.0 control register de? nitions 0x0echroma (v) gain register , lower byte (sa t_v_lo) bt829b v ideostr eam ii decoders d829bdsa 0x0echroma (v) gain register , lower byte (sa t_v_lo) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0xb4. sa t_v_lo(0) is the lsb. sa t_v_msb in the contr ol re gister and sa t_v_lo concatenate to gi v e a 9-bit re gister (sa t_v). this re gister is used to add a g ain adjustment to the v -component of the video signal. by ad- justing the u and v color components of the video stream by the same amount, the saturation is adjusted. f or nor - mal saturation adjustment, the g ain in both the color dif ference paths must be the same (i.e., the ratio between the v alue in the u g ain re gister and the v alue in the v g ain re gister should be k ept constant at the def ault po wer -up ratio). when changing the saturation, if the sa t_v_msb bit is altered, care must be tak en to ensure that the other bits in the contr ol re gister are not af fected. sa t_v_lo 7 6 5 4 3 2 1 0 sa t_v_lo 1 0 1 1 0 1 0 0 decimal value hex value % of original signal 511 0x1ff 283.89% 510 0x1fe 283.33% . . . . . . 181 0x0b5 100.56% 180 0x0b4 100.00% . . . . . . 128 0x080 71.11% . . . . . . 1 0x001 0.56% 0 0x000 0.00%
91 4.0 control register de? nitions 0x0fhue control register (hue) bt829b v ideostr eam ii decoders d829bdsa 0x0fhue control register (hue) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. hue(0) is the lsb. hue adjustment in v olv es the addition of a tw o s complement number to the demodulating subcarrier phase. hue can be adjusted in 256 steps in the range C90? to +89.3?, in increments of 0.7?. an asterisk indicates the def ault option. hue 7 6 5 4 3 2 1 0 hue 0 0 0 0 0 0 0 0 hex value binary value subcarrier reference changed by resulting hue changed by 0x80 1000 0000 C90? +90? 0x81 1000 0001 C89.3? +89.3? . . . . . . . . 0xff 1111 1111 C0.7? +0.7? 0x00* 0000 0000 00? 00? 0x01 0000 0001 +0.7? C0.7? . . . . . . . . 0x7e 0111 1110 +88.6? C88.6? 0x7f 0111 1111 +89.3? C89.3?
92 4.0 control register de? nitions 0x10 sc loop control (scloop) bt829b v ideostr eam ii decoders d829bdsa 0x10 sc loop control (scloop) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. a ccel is the lsb. an asterisk indicates the def ault option. peak this bit determines whether the normal luma lo w pass ? lters are implemented via the hfil t bits, or whether the peaking ? lters are implemented. the ldec bit in the control re gister must be programmed to zero to use these ? lters. 0* = normal luma lo w pass ? ltering 1 = use luma peaking ? lters cagc this bit controls the chroma a gc function. when enabled, chroma a gc will compensate for non-standard chroma le v els. the compensation is achie v ed by multiplying the incoming chroma signal by a v alue in the range of 0.5 to 2.0. 0* = chroma a gc disabled 1 = chroma a gc enabled ckill this bit determines whether the lo w color detector and remo v al circuitry is enabled. 0* = lo w color detection and remo v al disabled 1 = lo w color detection and remo v al enabled hfil t these bits control the con? guration of the optional 6-tap horizontal lo w-p ass filter . the auto f ormat mode determines the appropriate lo w-pass ? lter based on the selected horizontal scal- ing ratio. t o use these ? lters, the ldec bit in the contr ol re gister must be programmed to zero. 00* = auto f ormatif auto f ormat is selected when horizontally scaling between full resolution and half resolution, no ? ltering is selected. when scaling between one-half and one-third resolution, the cif ? lter is used. when scaling between one- third and one-se v enth resolution, the qcif ? lter is used; at less than one-se v enth resolution, the icon ? lter is used. 01 = cif 10 = qcif (when decoding secam video, this ? lter must be enabled.) 11 = icon if the peak bit is set to logical 1, the hfil t bits determine which peaking ? lter is selected. 00 = maximum peaking response 01 = medium peaking response 10 = lo w peaking response 11 = minimum peaking response reser ved these bits must be set to zero. 7 6 5 4 3 2 1 0 peak cagc ckill hfil t reser ved 0 0 0 0 0 0 0 0
93 4.0 control register de? nitions 0x11white crush up count register (wc_up) bt829b v ideostr eam ii decoders d829bdsa 0x11white crush up count register (wc_up) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0xcf . upcnt(0) is the lsb. majs these bits determine the majority comparison point for the white crush up function. 00 = 3/4 of maximum luma v alue 01 = 1/2 of maximum luma v alue 10 = 1/4 of maximum luma v alue 11* = automatic upcnt the v alue programmed in these bits accumulates once per ? eld or frame when the majority of the pix els in the acti v e re gion of the image are belo w a selected v alue. the accumulated v alue determines the e xtent to which the a gc v alue needs to be raised. this k eeps the sync le v el proportionate with the white le v el. the upcnt v alue is assumed positi v e: 3f = 63 3e = 62 : : : . . . 00 = 0 7 6 5 4 3 2 1 0 majs upcnt 1 1 0 0 1 1 1 1
94 4.0 control register de? nitions 0x12output format register (oform) bt829b v ideostr eam ii decoders d829bdsa 0x12output format register (oform) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x06. oes(0) is the lsb. an asterisk indicates the def ault option. range luma output rangethis bit determines the range for the luminance output on the bt829a. the range must be limited when using the control codes as video timing. 0* = normal operation (luma range 16C253, chroma range 2C253) y=16 is black (pedestal) cr , cb=128 is zero color information 1 = full-range output (luma range 0C255, chroma range 2C253) y=0 is black (pedestal) cr , cb=128 is zero color information core luma coringthese bits control the coring v alue used by the bt829a. when coring is acti v e and the total luminance le v el is belo w the limit programmed into these bits, the luminance sig- nal is truncated to zero. 00* = 0x00 no coring 01 = 8 10 = 16 11 = 32 vbi_frame this bit enables the vbi frame output mode. in the vbi frame output mode, e v ery line con- sists of un? ltered 8*fsc non-image data. this bit supersedes bit vbien in the vtc re gister . vbifmt (also in vtc) w orks in both vbi frame and line output modes. 0* = vbi frame output mode disabled 1 = vbi frame output mode enabled code code control disablethis bit determines whether control codes are output with the video data. spi mode 2 requires this bit to be programmed with a logical 1. when control codes are inserted into the data stream, the e xternal control signals are still a v ailable. 0* = disable control code insertion 1 = enable control code insertion len 8- or 16-bit f ormatthis bit determines the output data format. in 8-bit mode, the data is out- put on vd[15:8]. 0 = 8-bit ycrcb 4:2:2 output stream 1* = 16-bit ycrcb 4:2:2 output stream 7 6 5 4 3 2 1 0 range core vbi_frame code len oes 0 0 0 0 0 1 1 0 y/cr/cb[7] y/cr/cb[0] y[7] y[0] vd[15] vd[8] vd[7] vd[0] cr/cb[7] cr/cb[0] vd 16-bit 8-bit
95 4.0 control register de? nitions 0x13v ertical scaling register , upper byte (vscale_hi) bt829b v ideostr eam ii decoders d829bdsa oes oes[1] and oes[0] control the output three-states when the oe pin or the outen bit (vpole bit 7) is asserted. the pins are di vided into three groups: timing ( hreset , vreset , a ctive, v a ctive, cbfla g, d v alid, and field), clocks (clkx1, clkx2 and qclk), and data (vd[15:0]). ccv alid cannot output three-states. 00 = three-state timing and data only 01 = three-state data only 10 = three-state timing, data and clocks 11 = three-state clocks and data only 0x13v ertical scaling register , upper byte (vscale_hi) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x60. an asterisk indicates the def ault option. ycomb luma comb enablewhen enabled, the luma comb ? lter performs a weighted a v erage on tw o, three, four , or ? v e lines of luminance data. the coef ? cients used for the a v erage are ? x ed and no interpolation is performed. the number of lines used for the luma comb ? lter is deter - mined by the vfil t bits in the vtc re gister . when disabled by a logical 0, ? ltering and full v ertical interpolation is performed based upon the v alue programmed into the vscale re gis- ter . the luma comb ? lter cannot be enabled on the bt827a. 0* = v ertical lo w-pass ? ltering and v ertical interpolation 1 = v ertical lo w-pass ? ltering only comb chroma comb enablethis bit determines whether the chroma comb is included in the data path. if enabled, a full line store is used to a v erage adjacent lines of color information. this reduces cross-color artif acts. 0 = chroma comb disabled 1* = chroma comb enabled int interlacethis bit is programmed to indicate whether the incoming video is interlaced or non- interlaced. f or e xample, when using the full frame as input for v ertical scaling, this bit should be programmed high. if using a single ? eld for v ertical scaling, this bit should be programmed lo w . single ? eld scaling is normally used when scaling belo w cif resolution and when output- ting to a non-interlaced monitor . using a single ? eld reduces motion artif acts. 0 = non-interlace vs 1* = interlace vs vscale_hi v ertical scaling ratiothese ? v e bits represent the most signi? cant portion of the 13-bit v er - tical scaling ratio re gister . care must be tak en to a v oid altering the contents of the line, comb, and int bits when adjusting the scaling ratio. 7 6 5 4 3 2 1 0 ycomb comb int vscale_hi 0 1 1 0 0 0 0 0
96 4.0 control register de? nitions 0x14v ertical scaling register , lower byte (vscale_lo) bt829b v ideostr eam ii decoders d829bdsa 0x14v ertical scaling register , lower byte (vscale_lo) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. vscale_lo v ertical scaling ratiothese eight bits represent the lsbyte of the 13-bit v ertical scaling ratio re gister . the y are concatenated with 5 bits in vscale_hi. the follo wing equation is used to determine the v alue for this re gister: f or e xample, to scale p al/secam input to square pix el qcif , the total number of v ertical lines is 156: 0x15t est control register (test) this control re gister is reserv ed for putting the part into test mode. write operation to this re gister may cause undetermined beha vior and should not be attempted. a read c ycle from this re gister returns 0x01, and only a write of 0x01 is permitted. 7 6 5 4 3 2 1 0 vscale_lo 0 0 0 0 0 0 0 0 vscale = ( 0x10000 C { [ ( scaling_ratio ) C 1] * 512 } ) & 0x1fff vscale = ( 0x10000 C { [ ( 4/1 ) C1 ] * 512 } ) & 0x1fff = 0x1a00
97 4.0 control register de? nitions 0x16video t iming polarity register (vpole) bt829b v ideostr eam ii decoders d829bdsa 0x16video t iming polarity register (vpole) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. an asterisk indicates the def ault option. outen three-states the pins de? ned by oes in the oform re gister . the af fected pins are: vd[15:0], hreset , vreset , a ctive, v a ctive, d v alid, cbfla g, field, qclk, clkx1, and clkx2. when pin 85 is a logical 0 0* = enable outputs 1 = three-state outputs when pin 85 is a logical 1 0* = three-state outputs 1 = enable outputs dv alid 0* = d v alid pin: acti v e high 1 = d v alid pin: acti v e lo w v active 0* = v a ctive pin: acti v e high 1 = v a ctive pin: acti v e lo w cbflag 0* = cbfla g pin: acti v e high 1 = cbfla g pin: acti v e lo w field 0* = field pin: high indicates odd ? eld 1 = field pin: high indicates e v en ? eld active 0* = a ctive pin: acti v e high 1 = a ctive pin: acti v e lo w hreset 0* = hreset pin: acti v e lo w 1 = hreset pin: acti v e high vreset 0* = vreset pin: acti v e lo w 1 = vreset pin: acti v e high 7 6 5 4 3 2 1 0 out_en dv alid v active cbflag field active hreset vreset 0 0 0 0 0 0 0 0
98 4.0 control register de? nitions 0x17id code register (idcode) bt829b v ideostr eam ii decoders d829bdsa 0x17id code register (idcode) this control re gister may be read by the mpu at an y time. p ar t_rev(0) is the lsb. p ar t_id 1110 = bt829a p art id code 1100 = bt827a p art id code p ar t_rev 0x0 C 0xf = current re vision id code 0x18agc delay register (adela y) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x68. adela y this re gister indicates the a gc g ate delay for back-porch sampling. the follo wing equation should be used to determine the v alue for this re gister: f or e xample, for an ntsc input signal: 7 6 5 4 3 2 1 0 p ar t_id p ar t_rev 1 1 1 0 0 0 0 0 7 6 5 4 3 2 1 0 adela y 0 1 1 0 1 0 0 0 adelay = ( 6.8 m s * f clkx1 ) + 7 adelay = ( 6.8 m s * 14.32 mhz ) + 7 = 104 (0x68)
99 4.0 control register de? nitions 0x19burst delay register (bdela y) bt829b v ideostr eam ii decoders d829bdsa 0x19burst delay register (bdela y) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x5d. bdela y(0) is the lsb. bdela y this re gister indicates the b urst g ate delay for sub-carrier sampling. the follo wing equation should be used to determine the v alue for this re gister: f or e xample, for an ntsc input signal: 7 6 5 4 3 2 1 0 bdela y 0 1 0 1 1 1 0 1 bdelay = ( 6.5 m s * f clkx1 ) bdelay = ( 6.5 m s * 14.32 mhz ) = 93 (0x5d)
100 4.0 control register de? nitions 0x1aadc interface register (adc) bt829b v ideostr eam ii decoders d829bdsa 0x1aadc interface register (adc) this control re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x82. reserv ed is the lsb. an asterisk indicates the def ault option. reser ved these bits should only be written with bit 7 set at a logical 1 and bit 6 set at a logical 0. sync_t this bit de? nes the v oltage le v el for which the sync signal can be detected. 0* = analog syncdet threshold high (~125 mv) 1 = analog syncdet threshold lo w (~75 mv) agc_en this bit controls the a gc function. when disabled, refout is not dri v en, and an e xternal reference v oltage must be pro vided. when enabled, refout is dri v en to control the a/d reference v oltage. 0* = a gc enabled 1 = a gc disabled clk_sleep when this bit is set at a logical 1, the system clock is po wered do wn, b ut the output clocks (clkx1 and clkx2) are still running, and the i 2 c re gisters are still accessible. reco v ery time is approximately one second. 0* = normal clock operation 1 = shut do wn the system clock (po wer do wn) y_sleep this bit enables the luma adc to operate in sleep mode. 0* = normal y adc operation 1 = sleep y adc operation c_sleep this bit enables the chroma adc to operate in sleep mode. 0 = normal c adc operation 1* = sleep c adc operation crush this bit enables white cr ush mode, and must be written with a logical 0. 0* = normal sync le v el to white le v el 1 = enable white cr ush mode to compensate for nonstandard sync to white video relationship 7 6 5 4 3 2 1 0 reser ved sync_t agc_en clk_sleep y_sleep c_sleep crush 1 0 0 0 0 0 1 0
101 4.0 control register de? nitions 0x1bvideo t iming control (vtc) bt829b v ideostr eam ii decoders d829bdsa 0x1bvideo t iming control (vtc) this re gister may be written to or read by the mpu at an y time. upon reset, it is initialized to 0x00. vfil t(0) is the lsb. an asterisk indicates the def ault option. hsfmt this bit selects between a single-pix el-wide hreset and the standard 64-clock-wide hreset . 0* = hreset is 64 clkx1 c ycles wide 1 = hreset is 1 pix el wide actfmt this bit selects whether composite a ctive (ha ctive and v a ctive) or whether ha ctive only is output on the a ctive pin. 0* = a ctive is composite acti v e 1 = a ctive is horizontal acti v e clkga te this bit selects the signals that are g ated with clk to create qclk. if logical 0 is selected, the a ctive pin (composite a ctive or ha ctive) is used in g ating clk. 0* = clkx1 and clkx2 are g ated with d v alid and a ctive to create qclk 1 = clkx1 and clkx2 are g ated with d v alid to create qclk vbien this bit enables vbi data to be captured. 0* = do not capture vbi 1 = capture vbi vbifmt this bit determines the byte ordering for vbi data. 0* = pix el n on the vd[15:8] data b us, pix el n+1 on the vd[7:0] data b us 1 = pix el n+1 on the vd[15:8] data b us, pix el n on the vd[7:0] data b us (pix el n refers to the ? rst, third, ? fth, and so on, while pix el n+1 refers to the second, fourth, and sixth in a horizontal line of video) v alidfmt 0* = normal d v alid timing 1 = d v alid is the logical and of v alid and a ctive, where a ctive is controlled by the a ctfmt bit. also, the qclk signal will free turn and is an in v erted v ersion of clkx1 or clkx2, depending upon whether 8- or 16-bit pix el output format is selected. 7 6 5 4 3 2 1 0 hsfmt actfmt clkga te vbien vbifmt v alidfmt vfil t 0 0 0 0 0 0 0 0
102 4.0 control register de? nitions 0x1bvideo t iming control (vtc) bt829b v ideostr eam ii decoders d829bdsa vfil t these bits control the number of taps in the v ertical scaling filter . the number of taps must be chosen in conjunction with the horizontal scale f actor to ensure that the needed data does not o v er? o w the internal fifo. if the ycomb bit in the vscale_hi re gister is set at a logical 1, the follo wing settings and equations apply: 00* = 2-tap a v ailable at all resolutions. 01 = 3-tap only a v ailable when scaling to less than 385 horizontal acti v e pix els for p al, or 361 for ntsc (cif or smaller). 10 = 4-tap only a v ailable when scaling to less than 193 horizontal acti v e pix els for p al, or 181 for ntsc (qcif or smaller). 11 = 5-tap only a v ailable when scaling to less than 193 horizontal acti v e pix els for p al, or 181 for ntsc (qcif or smaller). if the ycomb bit in the vscale_hi re gister is set at a logical 0, the follo w- ing settings and equations apply: 00* = 2-tap interpolation only . a v ailable at all resolutions. 01 = 2-tap and 2-tap interpolation. only a v ailable when scaling to less than 385 horizontal acti v e pix els for p al, or 361 for ntsc (cif or smaller). 10 = 3-tap and 2-tap interpolation. only a v ailable when scaling to less than 193 horizontal acti v e pix els for p al, or 181 for ntsc (qcif or smaller). 11 = 4-tap and 2-tap interpolation. only a v ailable when scaling to less than 193 horizontal acti v e pix els for p al, or 181 for ntsc (qcif or smaller). note: the bt827a can only be used with a vfil t v alue of 00, because it does not ha v e a v ertical scaling ? lter . 1 2 - - - 1 z 1 C + ( ) 1 4 - - - 1 2 z 1 C z 2 C + + ( ) 1 8 - - - 1 3 z 1 C 3 z 2 C z 3 C + + + ( ) 1 16 - - - - - - 1 4 z 1 C 6 z 2 C 4 z 3 C z 4 C + + + + ( ) 1 2 - - - 1 z 1 C + ( ) 1 4 - - - 1 2 z 1 C z 2 C + + ( ) 1 8 - - - 1 3 z 1 C 3 z 2 C z 3 C + + + ( )
103 4.0 control register de? nitions 0x1cextended data ser vice/closed caption status register bt829b v ideostr eam ii decoders d829bdsa 0x1cextended data ser vice/closed caption status register (cc_st a tus) this re gister may be written or read by the mpu at an y time. upon reset, the v alue of re gister bits 7, 1, and 0 are indeterminate because their status depends on the incoming cc/eds data. ha ving re gister bits 6, 5, and 4 at their reset v alue causes the cc/eds circuitry to be po wered do wn. lo _hi is the lsb. an asterisk indicates the def ault option. p arity_err this bit corresponds to the current w ord in cc_d a t a. 0 = no error 1 = odd parity error note: closed caption data is transmitted using odd parity . ccv alid_en this bit serv es as a mask for the ccv alid interrupts pin. 0 = disabled ccv alid interrupts pin 1 = enabled ccv alid interrupts pin eds this bit determines whether eds data is written into the cc_d a t a fifo. 0* = eds data is not written into the cc_d a t a fifo 1 = eds data is written into the cc_d a t a fifo cc this bit determines whether cc data is written into the cc_d a t a fifo. 0* = cc data is not written into the cc_d a t a fifo 1 = cc data is written into the cc_d a t a fifo or this bit indicates the cc_d a t a fifo is full and that eds or cc data has been lost. this bit is read only . on reset or read of cc_d a t a, this bit is set to zero. 0 = an o v er? o w has not occurred since this bit w as last reset 1 = an o v er? o w has occurred da cc/eds data a v ailable. this bit indicates whether v alid data e xists in the cc_d a t a fifo. this bit is read only . on reset, this bit is set to zero. 0 = fifo is empty 1 = one or more bytes a v ailable cc _eds this bit indicates whether a cc byte or an eds byte is in the cc_d a t a re gister . after the cc_d a t a re gister is read, this bit is automatically updated. this bit is read only . on reset, this bit is not v alid. 0 = closed caption byte in cc_d a t a 1 = extended data service byte in cc_d a t a lo _hi cc/eds data are output in 16-bit w ords. this bit indicates whether the lo w or high byte is located in the cc_d a t a re gister . this bit is read only . on reset, this bit is not v alid. 0 = lo w byte is in the cc_d a t a re gister 1 = high byte is in the cc_d a t a re gister 7 6 5 4 3 2 1 0 p arity_err ccv alid_en eds cc or da cc _eds lo _hi x 1 0 0 0 0 x x
104 4.0 control register de? nitions 0x1dextended data ser vice/closed caption data register bt829b v ideostr eam ii decoders d829bdsa 0x1dextended data ser vice/closed caption data register (cc_da t a) the cc-d a t a re gister is read only and can be read by the mpu at an y time. an y writes to this re gister are ignored. upon reset, the v alue of the bits in this re gister are indeterminate because their status depends on the incoming cc/eds data. cc_d a t a(0) is the lsb. cc_da t a the lo w or high data byte transmitted in a closed caption or e xtended data service line. 0x1ewhite crush down count register (wc_dn) this control re gister may be written to or read by the mpu at an y time. upon reset, the v alue of the re gister bits is initialized to 0x7f . dncnt(0) is the lsb. this re gister is programmed with a tw o s complement number . ver ten 0* = normal operation 1 = adds v ertical detection algorithm to reject noise causing f alse v ertical syncs. wcframe this bit programs the rate at which the dncnt and upcnt v alues are accumulated. 0 = once-per -? eld 1 = once-per -frame dncnt the v alue programmed in these bits accumulates at a rate of once-per -? eld or frame. the accu- mulated v alue determines the e xtent to which the a gc v alue needs to be lo wered to k eep the sync le v el proportionate to the white le v el. the dncnt v alue is assumed ne g ati v e: 3f = C1 3e = C2 : : : . . . 00 = C64 0x1fsoftware reset register (sreset) this command re gister can be written at an y time. read c ycles to this re gister return an unde? ned v alue. a data write c ycle to this re gister resets the de vice to the def ault state (indicated in the command re gister de? nitions by an asterisk). writing an y data v alue into this address resets the de vice. 7 6 5 4 3 2 1 0 cc_da t a x x x x x x x x 7 6 5 4 3 2 1 0 ver ten wcframe dncnt 0 1 1 1 1 1 1 1
105 4.0 control register de? nitions 0x3fprogrammable i/o register (p_io) bt829b v ideostr eam ii decoders d829bdsa 0x3fprogrammable i/o register (p_io) this control re gister may be written to or read by the mpu at an y time. upon reset, the v alue of the re gister bits is initialized to 0x00. out_0 is the lsb. while in 8-bit output mode (spi-8), the vd[7:0] pins are completely asynchronous. in[3:0] represent the digital le v els input on vd[7:4], while the v alues programmed into out[3:0] represent the output on vd[3:0] in[3:0] these input bits can be used to monitor e xternal signals from vd[7:4]. the programmable i/o re gister is only accessible in the 8-bit 4:2:2 ycrcb output mode (len = 0). when not in 8- bit output mode, the v alues returned by the in[3:0] bits are not v alid. out[3:0] these output bits can be programmed to output miscellaneous additional signals from the video decoder on vd[3:0]. the programmable i/o re gister is only accessible in the 8-bit 4:2:2 ycrcb output mode. when not in the 8-bit output mode, the out[3:0] bits are set to logical 1. 7 6 5 4 3 2 1 0 in_3 in_2 in_1 in_0 out_3 out_2 out_1 out_0 0 0 0 0 0 0 0 0
106 4.0 control register de? nitions 0x3fprogrammable i/o register (p_io) bt829b v ideostr eam ii decoders d829bdsa
107 d829bdsa 5.0 parametric information 5.1 dc electrical parameters t able 5-1. recommended operating conditions parameter symbol min typ max units power supply analog v aa 4.75 5.00 5.25 v power supply 5.0 v digital v dd 4.75 5.00 5.25 v power supply 3.3 v digital v ddo 3.00 3.3 3.6 v maximum d |v dd C v aa | 0.5 v mux0, mux1 and mux2 input range (ac coupling required) 0.5 1.00 2.00 v vin amplitude range (ac coupling required) 0.5 1.00 2.00 v ambient operating t emperature t a 0 +70 ?c
108 5.0 parametric information 5.1 dc electrical parameters bt829b/827b v ideostr eam ii decoders d829bdsa t able 5-2. absolute maximum ratings parameter symbol min typ max units v aa (measured to agnd) 7.00 v v dd (measured to dgnd) 7.00 v v oltage on any signal pin (see the note below) dgnd C 0.5 v dd + 0.5 v analog input v oltage agnd C 0.5 v aa + 0.5 v storage t emperature t s C65 +150 ?c junction t emperature t j +125 ?c v apor phase soldering (15 seconds) t vsol +220 ?c note: stresses above those listed may cause permanent damage to the device. this is a stress rating only, and functional operation at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device employs high-impedance cmos devices on all signal pins. it must be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v, or drops below ground by more than 0.5 v, can induce destructive latch-up. t able 5-3. dc characteristics (3.3 v digital i/o operation) parameter symbol min typ max units digital inputs input high v oltage (ttl) v ih 2.0 v ddo + 0.5 v input low v oltage (ttl) v il 0.8 v input high v oltage (xt0i, xt1i,) v ih 2.3 v ddo + 0.5 v input low v oltage (xt0i, xt1i,) v il gnd C 0.5 1.0 v input high current (v in =v dd ) i ih 10 m a input low current (v in =gnd) i il C10 m a input capacitance (f=1 mhz, v in =2.4 v) c in pf input high v oltage (numxt al, i2ccs) v ih 2.5 v digital outputs output high v oltage (i oh = C400 m a) v oh 2.4 v ddo v output low v oltage (i ol = 3.2 ma) v ol 0.4 v three-state current i oz 10 m a output capacitance c o 5 pf analog pin input capacitance c a 5 pf
109 5.0 parametric information 5.1 dc electrical parameters bt829b/827b v ideostr eam ii decoders d829bdsa t able 5-4. dc characteristics (5 v only operation) parameter symbol min typ max units digital inputs input high v oltage (ttl) v ih 2.0 v dd + 0.5 v input low v oltage (ttl) v il 0.8 v input high v oltage (xt0i, xt1i,) v ih 3.5 v dd + 0.5 v input low v oltage (xt0i, xt1i,) v il gnd C 0.5 1.5 v input high current (v in =v dd ) i ih 10 m a input low current (v in =gnd) i il C10 m a input capacitance (f=1 mhz, v in =2.4 v) c in 5 pf digital outputs output high v oltage (i oh = C400 m a) v oh 2.4 v dd v output low v oltage (i ol = 3.2 ma) v ol 0.4 v three-state current i oz 10 m a output capacitance c o 5 pf analog pin input capacitance c a 5 pf
110 5.0 parametric information 5.2 ac electrical parameters bt829b/827b v ideostr eam ii decoders d829bdsa 5.2 ac electrical parameters t able 5-5. clock t iming parameters (1 of 2) parameter symbol min typ max units ntsc: clkx1 rate clkx2 rate (50 ppm sour ce required) f s1 f s2 14.318180 28.636360 mhz mhz p al/secam: clkx1 rate clkx2 rate (50 ppm sour ce required) f s1 f s2 17.734475 35.468950 mhz mhz xt0 and xt1 inputs cycle t ime high t ime low t ime 1 2 3 28.2 12 12 ns ns ns
111 5.0 parametric information 5.2 ac electrical parameters bt829b/827b v ideostr eam ii decoders d829bdsa clkx1 duty cycle clkx2 duty cycle clkx2 to clkx1 delay clkx1 to data delay clkx2 to data delay clkx1 (falling edge) to qclk (rising edge) clkx2 (falling edge) to qclk (rising edge) 8-bit mode (1) data to qclk (rising edge) delay qclk (rising edge) to data delay 16-bit mode (1) data to qclk (rising edge) delay qclk (rising edge) to data delay 4 5 6 41 42 7b 8b 7a 8a 45 40 0 3 3 0 0 5 15 14 25 55 60 2 11 (25) (2) 11 (25) (2) 8 8 % % ns ns ns ns ns ns ns ns ns notes: (1). because qclk is generated with a gated version of clkx1 or clkx2, the timing in symbols 7 and 8 are subject to changes in the duty cycle of clkx1 and clkx2. if crystals are used as clock sources for the bt829a, the duty cycle is symmetric. this assumption is used to generate the timing numbers shown in 7 and 8. for non-symmetric clock sources, use the following equations: (2). parenthesis indicate max clkx1/clkx2 to data delay when using v ddo = 3.3 v . t able 5-5. clock t iming parameters (2 of 2) parameter symbol min typ max units data to qclk (setup) 16-bit mode xtal period + clkx1 to qclk (max) - clkx1 to data (max) or symbol 1 + symbol 41 (max) - symbol 5 (max) ntsc: 34.9 ns + 8 ns - 11 ns = 31.9 ns p al: 28.2 ns + 8 ns -11 ns = 25.2 ns qclk to data (hold) 16-bit mode xtal period - clkx1 to qclk (min) + clkx1 to data (min) or symbol 1 - symbol 41 (min) + symbol 5 (min) ntsc: 34.9 ns - 0 ns + 3 ns = 37.9 ns p al: 28.3 ns - 0 ns + 3 ns = 31.3 ns data to qclk (setup) 8-bit mode (xtal period)/2 + clkx2 to qclk (max) - clkx2 to data (max) or (symbol 1)/2 + symbol 42 (max) - symbol 6 (max) ntsc: 17.5 ns + 8ns - 11 ns = 14.5 ns p al: 14.1 ns + 8 ns - 11 ns = 11.1 ns qclk to data (hold) 8-bit mode (xtal period)/2 - clkx2 to qclk (min) + clkx2 to data (min) or (symbol 1)/2 - symbol 42 (min) + symbol 6 (min) ntsc: 17.5 ns - 0 ns + 3 ns = 20.5 ns p al: 14.1 ns - 0 ns + 3 ns = 17.1 ns
112 5.0 parametric information 5.2 ac electrical parameters bt829b/827b v ideostr eam ii decoders d829bdsa figure 5-1. clock t iming diagram xt0i clkx2 or xt1i clkx1 pix el and control data 1 2 3 4 6 5 qclk pix el and control data qclk 8a 7a 16-bit mode 8-bit mode 42 41 8b 7b t able 5-6. power supply current parameters (3 and 5 v operation) parameter symbol min typ max units supply current v aa =v dd =5.0v , f clkx2 =28.64 mhz, t=25?c v aa =v dd =5.25v , f clkx2 =35.47 mhz, t=70?c v aa =v dd =5.25v , f clkx2 =35.47 mhz, t=0?c supply current, power down i 170 65 250 280 ma ma ma ma t able 5-7. output enable t iming parameters parameter symbol min typ max units oe asserted to data bus driven oe asserted to data v alid oe negated to data bus not driven 9 10 11 0 100 100 ns ns ns rst low t ime 8 xt al cycles
113 5.0 parametric information 5.2 ac electrical parameters bt829b/827b v ideostr eam ii decoders d829bdsa figure 5-2. output enable t iming diagram oe 10 11 pix el, cloc k and control data 9 t able 5-8. jt ag t iming parameters parameter symbol min typ max units tms, tdi setup t ime tms, tdi hold t ime tck asserted to tdo v alid tck asserted to tdo driven tck negated to tdo three-stated tck low t ime tck high time 12 13 14 15 16 17 18 25 25 10 10 60 5 80 ns ns ns ns ns ns ns figure 5-3. jt ag t iming diagram 12 13 17 18 14 15 16 tdi, tms tck tdo t able 5-9. decoder performance parameters parameter symbol min typ max units horizontal lock range 7 % of line length fsc, lock-in range 800 hz gain range C6 6 db note: test conditions (unless otherwise specified): recommended operating conditions. ttl input values are 0C3 v, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for digital inputs and outputs. pixel and control data loads 30 pf and 3 10 pf. clkx1 and clkx2 loads 50 pf. control data includes cbflag, dvalid, active, vactive, hreset , vreset and field.
114 5.0 parametric information 5.3 package mechanical drawings bt829b/827b v ideostr eam ii decoders d829bdsa 5.3 package mechanical drawings figure 5-4. 100-pin pqfp package mechanical drawing
115 5.0 parametric information 5.4 revision histor y bt829b/827b v ideostr eam ii decoders d829bdsa 5.4 revision histor y t able 5-10. bt829b datasheet revision histor y revision date description a 03/27/98 engineering release

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